MOBILE PENTIUM
II PROCESSOR IN
MINI-CARTRIDGE PACKAGE AT 400 MHZ, 366 MHZ,
333 MHZ, 300PE MHZ, AND 266PE MHZ DATASHEET
Available at 400 MHz, 366 MHz, 333 MHz,
300PE MHz, and 266PE MHz
Supports the Intel Architecture with
Dynamic Execution
Integrated primary 16-Kbyte instruction
cache and 16-Kbyte write back data cache
Integrated second level cache (256 Kbytes)
Mini-cartridge packaging technology
— Supports thin form factor notebook
designs
— Exposed die enables more efficient heat
dissipation
Fully compatible with previous Intel
microprocessors
— Binary compatible with all applications
— Support for MMX™ technology
Power Management features
— Quick Start and Deep Sleep modes
provide extremely low power
dissipation
Low Power GTL+ processor system bus
interface
Integrated math co-processor
Integrated thermal diode and sensor
The Intel
mobile Pentium
II processor introduces a higher level of performance for today’s mobile
computing environment, including multimedia enhancements, and improved Internet and communications
1
capabilities. It provides an improved performance for applications running on advanced operating systems
such as Windows* 98. On top of its built-in power management capabilities, the Pentium II processor takes
advantage of software designed for Intel’s MMX technology to unleash enhanced color, smoother graphics,
and other multimedia and communications enhancements.
The mobile Pentium II processor may contain design defects or errors know as errata that may cause the
product to deviate from published specifications. Current characterized errata are available upon request.
1.
Refer to the
Mobile Pentium
II Processor Performance Brief
.
INTEL CORPORATION
ORDER NUMBER 245108-002
MOBILE PENTIUM
®
II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ DATASHEET
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in
Intel's terms and conditions of sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or
implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them. Contact your local sales office or your distributor to obtain the latest specifications before placing your
product order.
The mobile Pentium II mini-cartridge processor may contain design defects or errors known as errata that may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Third-party brands and names are the property of their respective ownersI
2
C is a two-wire communications bus/protocol developed by
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG
CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained by calling 1-800-548-4725 or by visiting Intel’s website at
http://www.intel.com.
Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel. Implementations of the I
2
C bus/protocol or the
SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Copyright © Intel Corporation 1999.
* Third party brands and names are the property of their respective owners.
ii
INTEL CORPORATION
MOBILE PENTIUM
®
II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300 MHZ, AND 266 MHZ DATASHEET
CONTENTS
PAGE
1. INTRODUCTION .............................................. 1
1.1 Overview.................................................... 2
1.2 Terminology ............................................... 2
1.3 References ................................................ 2
2. MOBILE PENTIUM II MINI-CARTRIDGE
PROCESSOR FEATURES............................... 4
2.1 New Features in the Mobile Pentium II Mini-
cartridge Processor .................................... 4
2.1.1 Integrated L2 Cache ......................... 4
2.1.2 TRST# Pull-down Requirement ........ 4
2.2 Power Management ................................... 4
2.2.1 Clock Control Architecture ................ 4
2.2.2 Normal State .................................... 6
2.2.3 Auto Halt State ................................. 6
2.2.4 STOP GRANT State ......................... 7
2.2.5 QUICK START State ........................ 7
2.2.6 HALT/GRANT SNOOP State............ 7
2.2.7 SLEEP State .................................... 7
2.2.8 Deep Sleep State ............................. 8
2.2.9 Operating System Implications of
Quick Start and Sleep States............ 8
2.3 Low Power GTL+ ....................................... 8
2.3.1 GTL+ Signals.................................... 9
2.4 Mobile Pentium II Mini-cartridge Processor
CPUID........................................................ 9
3. ELECTRICAL SPECIFICATIONS .................. 10
3.1 Processor System Signals ....................... 10
3.1.1 Test Access Port (TAP) Connection 11
3.1.2 Thermal Sensor .............................. 11
3.1.3 SMBus Pins.................................... 12
3.1.4 Catastrophic Thermal Protection .... 12
3.1.5 Unused Signals .............................. 12
3.1.6 Signal State in Low Power States ... 12
3.2 Power Supply Requirements .................... 12
3.2.1 Decoupling Recommendations ....... 12
3.2.2 Power Sequencing Requirements... 13
3.3
3.4
3.5
2.6
PAGE
System Bus Clock and Processor Clocking13
Maximum Ratings .................................... 14
DC Specifications..................................... 14
AC Specifications ..................................... 19
2.6.1 System Bus, Clock, APIC, TAP,
CMOS, and Open-drain AC
Specifications ................................. 19
4. SYSTEM SIGNAL SIMULATIONS ................. 32
4.1 System Bus Clock (BCLK) Signal Quality
Specifications........................................... 32
4.2 Low Power GTL+ Signal Quality
Specifications........................................... 34
4.3 Non-Low Power GTL+ Signal Quality
Specifications........................................... 36
4.3.1 Overshoot and Undershoot
Guidelines....................................... 36
4.3.2 Ringback Specification.................... 37
4.3.3 Settling Limit Guideline ................... 37
5. MECHANICAL SPECIFICATIONS ................. 39
5.1 Connector Mechanical Specifications....... 39
5.2 Mini-cartridge Assembly Mechanical
Specifications........................................... 39
5.2 Processor Pin Lists .................................. 46
6. THERMAL SPECIFICATIONS........................ 53
7. PROCESSOR INITIALIZATION AND
CONFIGURATION.......................................... 54
7.1 Description ............................................... 54
7.1.1 Quick Start Enable.......................... 54
7.1.2 System Bus Frequency................... 54
7.1.3 APIC Disable .................................. 54
7.2 Clock Frequencies and Ratios.................. 54
8. PROCESSOR INTERFACE............................ 55
8.1 Alphabetical Signal Reference ................. 55
8.2 Signal Summaries .................................... 62
INTEL CORPORATION
iii
MOBILE PENTIUM
®
II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ DATASHEET
LIST OF FIGURES
PAGE
Figure 1.1 Signal Groups of a Mobile Pentium II
Mini-cartridge Processor Based System1
Figure 2.1 Clock Control States............................. 5
Figure 3.1 Ramp Rate Requirement ..................... 13
Figure 3.2 BCLK Connector to Core Offset.......... 26
Figure 3.3 Generic Clock Waveform.................... 26
Figure 3.4 Valid Delay Timings............................ 27
Figure 3.5 Setup and Hold Timings ..................... 27
Figure 3.6 Reset and Configuration Timings........ 28
Figure 3.7 Power-on Reset Timings .................... 28
Figure 3.8 Test Timings (Boundary Scan) ........... 29
Figure 3.9 Test Reset Timings............................. 29
Figure 3.10 Quick Start and Deep Sleep Timing.. 30
Figure 3.11 Stop Grant, Sleep, and Deep Sleep
Timing................................................ 31
Figure 4.1 BCLK Generic Clock Waveform at the
Processor Core.................................. 33
Figure 4.2 BCLK Generic Clock Waveform at the
Processor Connector ......................... 34
Figure 4.3 Low to High, Low Power GTL+ Receiver
Ringback Tolerance ........................... 35
Figure 4.4 Non-GTL+ Overshoot/Undershoot and
Ringback............................................ 37
Figure 5.1 Mini-cartridge Cross Section View ...... 40
Figure 5.2. Mini-cartridge Assembly, Top Cover (in
mm) ................................................... 41
Figure 5.3 Mini-cartridge Assembly, Bottom Cover
and Sides (in mm) ............................. 42
Figure 5.4 Standoff and Connector Location, Top
View (in mm)...................................... 43
Figure 5.5. Mini-cartridge Assembly and Connector
Keep-out Location, Top View (in mm) 44
Figure 5.6 Mini-cartridge Cross Section with
Vertical Dimensions ........................... 45
Figure 8.1 PWRGOOD Relationship at Power-on 59
iv
INTEL CORPORATION
MOBILE PENTIUM
®
II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ DATASHEET
LIST OF TABLES
PAGE
Table 2.1 Clock State Characteristics.................... 6
Table 2.2 Mobile Pentium II Processor CPUID ....... 9
Table 2.3 Mobile Pentium II Processor CPUID
Cache and TLB Descriptors ................. 9
Table 3.1 System Signal Groups ......................... 10
Table 3.2 Recommended Resistors for Open-drain
Signals............................................... 11
Table3.3 Mobile Pentium II Mini-cartridge
Processor Absolute Maximum Ratings
.......................................................... 14
Table 3.4 Mobile Pentium II Processor Power
Specifications .................................... 15
Table 3.5 Mobile Pentium II Processor Power
Specifications .................................... 16
Table 3.6 Low Power GTL+ Signal Group DC
Specifications .................................... 17
Table 3.7 Low Power GTL+ Bus DC Specifications
.......................................................... 18
Table 3.8 Clock, APIC, TAP, CMOS, and Open-
drain Signal Group DC Specifications 18
Table 3.9 System Bus Clock AC Specifications... 19
®
Table 3.10 Valid Mobile Pentium II Mini-cartridge
Processor Frequencies ...................... 21
Table 3.11 Low Power GTL+ Signal Groups AC
Specifications .................................... 21
Table 3.12 CMOS and Open-drain Signal Groups
AC Specifications .............................. 22
Table 3.13 Reset Configuration AC Specifications
.......................................................... 22
Table 3.14 APIC Bus Signal AC Specifications ... 23
Table 3.15 TAP Signal AC Specifications............ 24
Table 3.16 Quick Start/Deep Sleep AC
Specifications .................................... 25
Table 3.17 Stop Grant/Sleep/Deep Sleep AC
Specifications .................................... 25
Table 4.1 BCLK Signal Quality Specifications at the
Processor Core.................................. 32
Table 4.2 BCLK Signal Quality Guidelines at the
Processor Connector ......................... 33
Table 4.3 Low Power GTL+ Signal Group Ringback
Specification at the Processor Core... 34
Table 4.4 Low Power GTL+ Signal Group Ringback
Guideline at the Processor Connector 36
PAGE
Table 4.5 Signal Ringback Specifications for Non-
GTL+ Signals at the Processor Core.. 38
Table 5.1 Mechanical Specifications.................... 40
Table 5.2. Mini-cartridge Vertical Dimensions ...... 45
Table 5.3 Mini-cartridge Vertical Dimension
Definitions .......................................... 46
Table 5.4 Pin Listing in Signal Name Order ......... 48
Table 6.1 Mobile Pentium II Processor Power
Specifications..................................... 53
Table 8.1 Voltage Identification Pin Encoding...... 62
Table 8.2 Input Signals ........................................ 63
Table 8.3 Output Signals ..................................... 64
Table 8.4 Input/Output Signals (Single Driver) ..... 64
Table 8.5. Input/Output Signals (Multiple Drivers) 65
INTEL CORPORATION
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