Integrated
Circuit
Systems, Inc.
ICS87608I
L
OW
V
OLTAGE
/L
OW
S
KEW
, 1:8 PCI/PCI-X
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
EATURES
•
Fully integrated PLL
•
Eight LVCMOS/LVTTL outputs, 15Ω typical output impedance
•
Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_IN clock input
•
Maximum output frequency: 166.67MHz
•
Maximum crystal input frequency: 38MHz
•
Maximum REF_IN input frequency: 41.67MHz
•
Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz
•
Separate feedback control for generating PCI / PCI-X
frequencies from a 16.66MHz or 20MHz crystal, or 25MHz
or 33.33MHz reference frequency
•
VCO range: 200MHz to 500MHz
•
Cycle-to-cycle jitter: 120ps (maximum), @ 3.3V
•
Period jitter, RMS: 20ps (maximum)
•
Output skew: 250ps (maximum)
•
Bank skew: 60ps (maximum)
•
Static phase offset: 160ps ± 160ps
•
Voltage Supply Modes:
V
DD
(core/inputs), V
DDA
(analog supply for PLL),
V
DDOA
(output bank A),
V
DDOB
(output bank B, REF_OUT, FB_OUT)
V
DD
/V
DDA
/V
DDOA
/V
DDOB
3.3/3.3/3.3/3.3
3.3/3.3/2.5/3.3
3.3/3.3/3.3/2.5
3.3/3.3/2.5/2.5
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
V
DDOB
G
ENERAL
D
ESCRIPTION
The ICS87608I has a selectable REF_CLK or
crystal input. The REF_CLK input accepts
HiPerClockS™
LVCMOS or LVTTL input levels. The ICS87608I
has a fully integrated PLL along with frequency
configurable clock and feedback outputs for
multiplying and regenerating clocks with “zero delay”.
IC
S
The ICS87608I is a 1:8 PCI/PCI-X Clock Generator and a
member of the HiPerClockS
TM
family of high performance clock
solutions from ICS. The ICS87608I has a selectable REF_CLK
or crystal input. The REF_CLK input accepts LVCMOS or
LVTTL input levels. The ICS87608I has a fully integrated PLL
along with frequency configurable clock and feedback outputs
for multiplying and regenerating clocks with “zero delay”. The
PLL’s VCO has an operating range of 250MHz-500MHz,
allowing this device to be used in a variety of general purpose
clocking applications. For PCI/PCI-X applications in particular,
the VCO frequency should be set to 400MHz. This can be
accomplished by supplying 33.33MHz, 25MHz, 20MHz, or
16.66MHz on the reference clock or crystal input and by
selecting ÷12, ÷16, ÷20, or ÷24, respectively as the feedback
divide value. The dividers on each of the two output banks
can then be independently configured to generate 33.33MHz
(÷12), 66.66MHz (÷6), 100MHz (÷4), or 133.33MHz (÷3).
The ICS87608I is characterized to operate with its core supply
at 3.3V and each bank supply at 3.3V or 2.5V. The ICS87608I
is packaged in a small 7x7mm body LQFP, making it ideal for
use in space-constrained applications.
P
IN
A
SSIGNMENT
REF_IN
V
DDOA
XTAL2
XTAL1
32 31 30 29 28 27 26 25
QA0
QA1
GND
QA2
QA3
V
DDOA
MR
DIV_SELA0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
DIV_SELA1
DIV_SELB0
DIV_SELB1
FBDIV_SEL0
FBDIV_SEL1
V
DD
FB_IN
GND
ICS87608I
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y package
Top View
XTAL_SEL
PLL_SEL
V
DDA
24
23
22
21
20
19
18
17
QB0
QB1
GND
QB2
QB3
V
DDOB
REF_OUT
FB_OUT
87608AYI
www.icst.com/products/hiperclocks.html
1
REV. C APRIL 28, 2006
Integrated
Circuit
Systems, Inc.
ICS87608I
L
OW
V
OLTAGE
/L
OW
S
KEW
, 1:8 PCI/PCI-X
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Type
Output
Power
Power
Input
Description
Bank A clock outputs. 15
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Power supply ground.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2,
4, 5
3, 16, 22
6, 32
7
8,
9,
10,
11
12,
13
14
15
17
18
19, 25
20, 21,
23, 24
26
27
28
29, 30
31
Name
QA0, QA1,
QA2, QA3
GN D
V
DDOA
MR
DIV_SELA0,
DIV_SELA1,
DIV_SELB0,
DIV_SELB1
FBDIV_SEL0,
FBDIV_SEL1
V
DD
FB_IN
FB_OUT
REF_OUT
V
DDOB
QB3, QB2,
QB1, QB0
PLL_SEL
V
DDA
XTAL_SEL
XTAL1,
XTAL2
REF_IN
Output supply pins for Bank A outputs.
Active HIGH Master Reset. When logic HIGH, the internal dividers
Pulldown are reset causing the outputs go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
Pulldown
Selects divide value for clock outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Input
Input
Power
Input
Output
Output
Power
Output
Input
Power
Input
Input
Input
Selects divide value for reference clock output and feedback output.
LVCMOS / LVTTL interface levels.
Core supply pin.
Feedback input to phase detector for generating clocks with
Pulldown
"zero delay". LVCMOS / LVTTL interface levels.
Feedback output. Connect to FB_IN. LVCMOS / LVTTL interface levels.
Pulldown
Reference clock output. LVCMOS / LVTTL interface levels.
Output supply pins for Bank B and REF_OUT, FB_OUT outputs.
Bank B clock outputs. 15
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
Analog supply pin. See Applications Note for filtering.
Selects between cr ystal oscillator or reference clock as the PLL
reference source. Selects XTAL inputs when HIGH. Selects REF_IN
when LOW. LVCMOS / LVTTL interface levels.
Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Pullup
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output); NOTE 1
Output Impedance
V
DD
, V
DDA
, V
DDOX
= 3.465V
V
DD
, V
DDA
= 3.465V; V
DDOX
= 2.625V
15
Test Conditions
Minimum Typical
4
51
51
9
11
Maximum
Units
pF
kΩ
kΩ
pF
pF
Ω
V
DDOX
denotes V
DDOA
and V
DDOB
.
87608AYI
www.icst.com/products/hiperclocks.html
3
REV. C APRIL 28, 2006
Integrated
Circuit
Systems, Inc.
ICS87608I
L
OW
V
OLTAGE
/L
OW
S
KEW
, 1:8 PCI/PCI-X
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDOX
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDOX
I
DD
I
DDA
I
DDOA
I
DDOB
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3. 3
3. 3
Maximum
3.465
3.465
3.465
185
15
20
20
Units
V
V
V
mA
mA
mA
mA
V
DDOX
denotes V
DDOA
, V
DDOB
.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDOX
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
MR, DIV_ SELx0, DIV_SELx1,
FBDIV_SEL0, FBDIV_SEL1,
Input
High Voltage XTAL_SEL, FB_IN, PLL_SEL
REF_IN
MR, DIV_ SELx0, DIV_SELx1,
FBDIV_SEL0, FBDIV_SEL1,
Input
Low Voltage XTAL_SEL, FB_IN, PLL_SEL
REF_IN
DIV_ SELx0, DIV_SELx1,
FBDIV_SEL0, FBDIV_SEL1,
Input
High Current MR, FB_IN
XTAL_SEL, PLL_SEL
DIV_ SELx0, DIV_SELx1,
FBDIV_SEL0, FBDIV_SEL1,
Input
MR, FB_IN
Low Current
XTAL_SEL, PLL_SEL
Output High Voltage; NOTE 1
Test Conditions
Minimum
2
2
-0.3
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V,
V
IN
= 0V
V
DD
= 3.465V,
V
IN
= 0V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 2.625V
-5
-150
2.6
1.8
0.5
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
IH
V
IL
I
IH
I
IL
V
OH
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DDOX
/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
87608AYI
www.icst.com/products/hiperclocks.html
5
REV. C APRIL 28, 2006
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