L
OW
S
KEW
,
÷2/4,÷4/6,
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87339-01 is a low skew, high performance
Differential-to-3.3V LVPECL / ECL Clock Generator/Divider.
The ICS87339-01 has one differential clock input pair. The
CLK, nCLK pair can accept most standard differential input
levels. The clock enable isinternally synchronized to
eliminate runt pulses on theoutputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS87339-01 ideal for clock distribution applications
demanding well defined performance and repeatability.
ICS87339-01
F
EATURES
•
Two divide by 2/4 differential 3.3V LVPECL outputs;
two divide by 4/6 differential 3.3V LVPECL outputs
•
One differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum input frequency: 1GHz
•
Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
•
Output skew: 35ps (maximum)
•
Part-to-part skew: 385ps (maximum)
•
Bank skew: Bank A - 30ps (maximum)
Bank B - 25ps (maximum)
•
Propagation delay: 2.1ns (maximum)
•
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.6V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.6V to -3V
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
DIV_SELA
QA0
nQA0
nCLK_EN
D
Q
LE
CLK
nCLK
QB0
nQB0
÷4, ÷6
÷2, ÷4
P
IN
A
SSIGNMENT
V
CC
nCLK_EN
DIV_SELB
CLK
nCLK
RESERVED
MR
V
CC
nc
DIV_SELA
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
V
EE
R
QA1
nQA1
ICS87339-01
20-Lead SOIC, M Package
7.5mm x 12.8mm x 2.25
package body
Top View
R
MR
DIV_SELB
QB1
nQB1
87339AM-01
www.idt.com
1
REV. B AUGUST 2, 2010
L
OW
S
KEW
,
÷2/4,÷4/6,
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 8, 20
2
3
4
5
6
Name
V
CC
nCLK_EN
DIV_SELB
CLK
nCLK
RESERVED
Power
Input
Input
Input
Input
Reser ve
Type
Description
Positive supply pins.
Pulldown Clock enable.
Selects divide value for Bank B outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
ICS87339-01
Inver ting differential clock input.
Reser ve pin.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs (Qx) to go low, and the inver ted outputs
7
MR
Input
Pulldown
(nQX) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
No connect.
9
nc
Unused
Selects divide value for Bank A outputs as described in Table 3.
10
DIV_SELA
Input
Pulldown
LVCMOS / LVTTL interface levels.
Power
Negative supply pin.
11
V
EE
12, 13
nQB1, QB1
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
14, 15
nQB0, QB0
Output
Differential output pair. LVPECL interface levels.
16, 17
nQA1, QA1
Output
18, 19
nQA0, QA0
Output
Differential output pair. LVPECL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
MR
1
0
0
0
0
0
nCLK_EN
X
1
0
0
0
0
DIV_SELA
X
X
0
0
1
1
DIV_SELB
X
X
0
1
0
1
QA0, QA1
LOW
Not Switching
÷2
÷2
÷4
÷4
HIGH
Not Switching
÷2
÷2
÷4
÷4
Outputs
nQA0, nQA1
QB0, QB1
LOW
Not Switching
÷4
÷6
÷4
÷6
nQB0, nQB1
HIGH
Not Switching
÷4
÷6
÷4
÷6
NOTE: After nCLK_EN switches, the clock outputs stop switching following a rising and falling input clock edge.
87339AM-01
www.idt.com
2
REV. B AUGUST 2, 2010
L
OW
S
KEW
,
÷2/4,÷4/6,
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
G
ENERATOR
ICS87339-01
CLK
t
RR
MR
Q (÷n)
F
IGURE
1A. MR T
IMING
D
IAGRAM
Disabled
CLK
nCLK
Enabled
nCLK_EN
QAx, QBx
nQAx, nQBx
F
IGURE
1B.
N
CLK_EN T
IMING
D
IAGRAM
87339AM-01
www.idt.com
3
REV. B AUGUST 2, 2010
L
OW
S
KEW
,
÷2/4,÷4/6,
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink/Source, I
BB
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
4.6V (LVPECL mode, V
EE
= 0)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (ECL mode, V
CC
= 0)
-0.5V to V
CC
+ 0.5 V
0.5V to V
EE
- 0.5V
50mA
100mA
± 0.5mA
-65°C to 150°C
46.2°C/W (0 lfpm)
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
ICS87339-01
Operating Temperature Range, TA -40°C to +85°C
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= 0°C
TO
70°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
105
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
nCLK_EN, MR,
DIV_SELA, DIV_SELB
nCLK_EN, MR,
DIV_SELA, DIV_SELB
V
IN
= V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
IN
= V
CC
= 3.6V
V
IN
= V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
-150
-5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
V
EE
+ 0.5
NOTE 1, 2
NOTE 1: For single ended applications
,
the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
87339AM-01
www.idt.com
4
REV. B AUGUST 2, 2010
L
OW
S
KEW
,
÷2/4,÷4/6,
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
G
ENERATOR
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= 0°C
TO
70°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
ICS87339-01
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay to Output; NOTE 1
Output Skew; NOTE 2, 5
Bank Skew; NOTE 3, 5
Bank A
Bank B
nCLK_EN to CLK
CLK to nCLK_EN
CLK
20% to 80%
350
100
400
550
100
600
CLK to Q (Diff)
1.6
20
20
12
Test Conditions
Minimum
Typical
Maximum
1
2.1
35
30
25
385
Units
GHz
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
t
sk(o)
t
sk(b)
t
sk(pp)
t
S
t
H
t
RR
t
PW
t
R /
t
F
Par t-to-Par t Skew; NOTE 4, 5
Setup Time
Hold Time
Reset Recovery Time
Minimum Pulse Width
Output Rise/Fall Time
odc
Output Duty Cycle
48
52
%
All data taken with outputs ÷4.
All parameters measured up to 1GHz unless noted otherwise.
This device does not add measureable jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
87339AM-01
www.idt.com
5
REV. B AUGUST 2, 2010
京公网安备 11010802033920号
EEWORLD
