Mixed-Signal Front End
for Broadband Applications
AD9878
FEATURES
Low cost 3.3 V CMOS MxFE™ for broadband applications
DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant
232 MHz quadrature digital upconverter
12-bit direct IF DAC (TxDAC+®)
Up to 65 MHz carrier frequency DDS
Programmable sampling clock rates
Analog Tx output level adjust
Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input
10-bit, 29 MSPS sampling ADC
8-bit ∑-∆ auxiliary DAC
Direct interface to AD832x family of PGA cable drivers
TxID[5:0]
FUNCTIONAL BLOCK DIAGRAM
I
Tx
Q
16
SINC
–1
12
DAC
Tx
DDS
Σ
-∆
SDIO
4
3
CONTROL REGISTERS
CA PORT
MCLK
PLL
IF10[4:0]
10
MUX
ADC
OSCIN
IF10 INPUT
Σ-∆
OUTPUT
12
ADC
MUX
Σ
IF12[11:0]
MUX
MUX
12
FLAG[2:1]
–
CLAMP
LEVEL
ADC
IF12B INPUT
VIDEO IN
APPLICATIONS
Cable set-top boxes
Cable and wireless modems
IF12A INPUT
03277-001
Figure 1.
GENERAL DESCRIPTION
The AD9878 is a single-supply, cable modem/set-top box,
mixed-signal front end. The device contains a transmit path
interpolation filter, a complete quadrature digital upconverter,
and a transmit DAC. The receive path contains dual 12-bit
ADCs and a 10-bit ADC. All internally required clocks and an
output system clock are generated by the phase-locked loop
(PLL) from a single crystal oscillator or clock input.
The transmit path interpolation filter provides an upsampling
factor of 16× with an output signal bandwidth up to 4.35 MHz.
Carrier frequencies up to 65 MHz with 26 bits of frequency tuning
resolution can be generated by the direct digital synthesizer
(DDS). The transmit DAC resolution is 12 bits and can run at
sampling rates as high as 232 MSPS. Analog output scaling from
0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when
reduced output levels are required.
The 12-bit ADCs provide excellent undersampling performance,
allowing this device to typically deliver better than 10 ENOBs
with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at
rates up to 29 MHz, allowing them to process wideband signals.
The AD9878 includes a programmable ∑-∆ DAC, which can be
used to control an external component such as a variable gain
amplifier (VGA) or a voltage controlled tuner.
The AD9878 also integrates a CA port that enables a host
processor to interface with the AD832x family of programmable
gain amplifier (PGA) cable drivers or industry equivalent via
the MxFE serial port (SPORT).
The AD9878 is available in a 100-lead, LQFP package. The
AD9878 is specified over the extended industrial (−40°C to
+85°C) temperature range.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
AD9878
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 4
Absolute Maximum Ratings............................................................ 7
Explanation of Test Levels ........................................................... 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 13
Register Bit Definitions.................................................................. 14
Register 0x00—Initialization .................................................... 15
Register 0x01—Clock Configuration....................................... 15
Register 0x02—Power-Down.................................................... 15
Register 0x03—Flag Control..................................................... 15
Register 0x04—∑-∆ Control Word........................................... 15
Register 0x07—Video Input Configuration............................ 16
Register 0x08—ADC Clock Configuration ............................ 16
Register 0x0C—Die Revision.................................................... 16
Register 0x0D—Tx Frequency Tuning Words LSBs.............. 16
Register 0x0E—DAC Gain Control ......................................... 16
Register 0x0F—Tx Path Configuration ................................... 16
Registers 0x10 Through 0x17—Burst Parameter................... 17
Serial Interface for Register Control ............................................ 18
General Operation of the Serial Interface ............................... 18
Instruction Byte .......................................................................... 18
Serial Interface Port Pin Descriptions ..................................... 18
MSB/LSB Transfers..................................................................... 19
Notes on Serial Port Operation ................................................ 19
Theory of Operation ...................................................................... 20
Transmit Path.............................................................................. 21
Data Assembler........................................................................... 21
Transmit Timing......................................................................... 21
Interpolation Filter..................................................................... 21
Half-Band Filters (HBFs) .......................................................... 21
Cascade Integrator Comb (CIC) Filter.................................... 21
Combined Filter Response........................................................ 21
Digital Upconverter ................................................................... 22
Tx Signal Level Considerations ................................................ 22
Tx Throughput and Latency ..................................................... 23
DAC.............................................................................................. 23
Programming the AD8321/AD8323 or
AD8322/AD8327/AD8238 Cable-Driver Amplifiers............ 23
OSCIN Clock Multiplier ........................................................... 24
Clock and Oscillator Circuitry ................................................. 24
Programmable Clock Output REFCLK .................................. 24
Power-Up Sequence ................................................................... 26
Reset ............................................................................................. 26
Transmit Power-Down .............................................................. 26
∑-∆ Outputs ................................................................................ 27
Receive Path (Rx) ....................................................................... 27
IF10 and IF12 ADC Operation ................................................ 27
ADC Voltage References ........................................................... 29
Video Input ................................................................................. 29
PCB Design Considerations.......................................................... 30
Component Placement .............................................................. 30
Power Planes and Decoupling .................................................. 30
Ground Planes ............................................................................ 30
Signal Routing............................................................................. 30
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
Rev. A | Page 2 of 36
AD9878
REVISION HISTORY
3/05—Rev. 0 to Rev. A
Changed OSCOUT to REFCLK.................................................. Universal
Changes to Electrical Characteristics ........................................................4
Changes to Pin Configuration and Function Descriptions....................8
Changes to ∑-∆ Output Signals (Figure 32)............................................27
Change to ∑-∆ RC Filter (Figure 33) .......................................................27
Changes to Evaluation PCB Schematic (Figure 38 and Figure 39)......31
Updated Outline Dimensions...................................................................36
Changes to Ordering Guide......................................................................36
5/03—Revision 0: Initial Version
Rev. A | Page 3 of 36
AD9878
ELECTRICAL CHARACTERISTICS
V
AS
= 3.3 V ± 5%, V
DS
= 3.3 V ± 10%, f
OSCIN
= 27 MHz, f
SYSCLK
= 216 MHz, f
MCLK
= 54 MHz (M = 8), ADC clock derived from OSCIN,
R
SET
= 4.02 kΩ, maximum. Fine gain, 75 Ω DAC load.
Table 1.
PARAMETER
OSCIN and XTAL CHARACTERISTICS
Frequency Range
Duty Cycle
Input Impedance
MCLK Cycle-to-Cycle Jitter (f
MCLK
derived from PLL)
Tx DAC CHARACTERISTICS
Maximum Sample Rate
Resolution
Full-Scale Output Current
Gain Error (Using Internal Reference)
Offset Error
Reference Voltage (REFIO Level)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Output Capacitance
Phase Noise @ 1 kHz Offset, 42 MHz Carrier
Output Voltage Compliance Range
Wideband SFDR
5 MHz Analog Output, I
OUT
= 10 mA
65 MHz Analog Output, I
OUT
= 10 mA
Narrow-Band SFDR (±1 MHz Window)
5 MHz Analog Output, I
OUT
= 10 mA
65 MHz Analog Output, I
OUT
= 10 mA
Tx MODULATOR CHARACTERISTICS
I/Q Offset
Pass-Band Amplitude Ripple (f < f
IQCLK
/8)
Pass-Band Amplitude Ripple (f < f
IQCLK
/4)
Stop-Band Response (f > f
IQCLK
× 3/4)
Tx GAIN CONTROL
Gain Step Size
Gain Step Error
Settling Time, 1% (Full-Scale Step)
10-BIT ADC CHARACTERISTICS
Resolution
Maximum Conversion Rate
Pipeline Delay
Analog Input
Input Voltage Range
Differential Input Impedance
Full Power Bandwidth
Dynamic Performance (A
IN
= −0.5 dBFS, f = 5 MHz)
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Reference Voltage Error, REFT10 to REFB10 (1.0 V)
Temp
Full
25°C
25°C
25°C
Full
N/A
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
N/A
Full
N/A
Full
25°C
25°C
Full
Full
Full
Full
Full
Test Level
II
II
III
III
II
N/A
II
I
I
I
III
III
III
III
II
II
II
II
II
II
II
II
II
III
III
III
N/A
II
N/A
II
III
III
II
II
II
II
I
57.6
9.3
65.7
Min
3
35
Typ
Max
29
65
Unit
MHz
%
MΩ||pF
ps rms
MHz
Bits
mA
% FS
% FS
V
LSB
LSB
pF
dBc/Hz
V
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
µs
Bits
MHz
ADC cycles
V
PPD
kΩ||pF
MHz
dB
Bits
dB
dB
mV
50
100||3
6
232
4
−2.0
1.18
12
10
−1
±1.0
1.23
±2.5
±8
5
−110
20
+2.0
1.28
−0.5
62.4
50.3
71
61
50
68
53.5
74
64
55
+1.5
±0.1
±0.5
−63
0.5
<0.05
1.8
10
29
4.5
2
4||2
90
59.7
9.6
−71.1
72.4
±4
−63.6
±100
Rev. A | Page 4 of 36
AD9878
PARAMETER
Dynamic Performance (A
IN
= −0.5 dBFS, f = 50 MHz)
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
12-BIT ADC CHARACTERISTICS
Resolution
Maximum Conversion Rate
Pipeline Delay
Analog Input
Input Voltage Range
Differential Input Impedance
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Input Referred Noise
Reference Voltage Error, REFT12 to REFB12 (1 V)
Dynamic Performance (A
IN
= −0.5 dBFS, f = 5 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOBs)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
ADC Sample Clock = PLL
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Dynamic Performance (A
IN
= −0.5 dBFS, f = 50 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Differential Phase
Differential Gain
VIDEO ADC PERFORMANCE (A
IN
= −0.5 dBFS, f = 5 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
CHANNEL-TO-CHANNEL ISOLATION
Tx DAC-to-ADC Isolation (5 MHz Analog Output)
Isolation Between Tx and 10-Bit ADC
Isolation Between Tx and 12-Bit ADCs
ADC-to-ADC Isolation (A
IN
= –0.5 dBFS, f = 5 MHz)
Isolation Between IF10 and IF12A/B
Isolation Between IF12A and IF12B
Temp
Full
Full
Full
Full
N/A
Full
N/A
Full
25°C
25°C
25°C
25°C
25°C
Full
Test Level
II
II
II
II
N/A
II
N/A
III
III
III
III
III
III
I
Min
54.8
8.8
56.9
Typ
57.8
9.3
−63.3
63.7
12
29
5.5
2
4||2
2.0
1.2
85
75
±16
Max
Unit
dB
Bits
dB
dB
Bits
MHz
ADC cycles
V
PPD
kΩ||pF
ns
ps rms
MHz
µV
mV
−56.9
−100
+100
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
II
II
II
II
II
II
II
II
II
II
61.0
9.8
64.2
62.8
60.4
9.74
62.4
62.7
67
10.8
66
−72.7
74.6
64.4
10.4
65.1
−72.7
74.6
−61.7
dB
Bits
dB
dB
dB
dB
Bits
dB
dB
dB
−61.8
Full
Full
Full
Full
Full
25°C
25°C
II
II
II
II
II
III
III
61.0
9.8
64.2
62.8
65.2
10.5
67.4
−72.8
74.6
<0.1
<1
−61.8
dB
Bits
dB
dB
dB
Degrees
LSB
Full
Full
Full
Full
II
II
II
II
46.7
54.3
45.9
53
63.2
−50.2
50
−45.9
dB
Bits
dB
dB
25°C
25°C
25°C
25°C
III
III
III
III
>60
>80
>85
>85
dB
dB
dB
dB
Rev. A | Page 5 of 36
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