AD9878-EB datasheet, PDF - EEWORLD Datasheet

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AD9878-EB: DescriptionMixed-Signal Front End for Broadband Applications; File Size732KB，36 Pages; ManufacturerADI; Websitehttps://www.analog.com

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AD9878-EB Overview

Mixed-Signal Front End for Broadband Applications

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Mixed-Signal Front End

for Broadband Applications

AD9878

FEATURES

Low cost 3.3 V CMOS MxFE™ for broadband applications

DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant

232 MHz quadrature digital upconverter

12-bit direct IF DAC (TxDAC+®)

Up to 65 MHz carrier frequency DDS

Programmable sampling clock rates

Analog Tx output level adjust

Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input

10-bit, 29 MSPS sampling ADC

8-bit ∑-∆ auxiliary DAC

Direct interface to AD832x family of PGA cable drivers

TxID[5:0]

FUNCTIONAL BLOCK DIAGRAM

SINC

–1

DAC

DDS

-∆

SDIO

CONTROL REGISTERS

CA PORT

MCLK

PLL

IF10[4:0]

MUX

ADC

OSCIN

IF10 INPUT

Σ-∆

OUTPUT

ADC

MUX

IF12[11:0]

MUX

FLAG[2:1]

–

CLAMP

LEVEL

ADC

IF12B INPUT

VIDEO IN

APPLICATIONS

Cable set-top boxes

Cable and wireless modems

IF12A INPUT

03277-001

Figure 1.

GENERAL DESCRIPTION

The AD9878 is a single-supply, cable modem/set-top box,

mixed-signal front end. The device contains a transmit path

interpolation filter, a complete quadrature digital upconverter,

and a transmit DAC. The receive path contains dual 12-bit

ADCs and a 10-bit ADC. All internally required clocks and an

output system clock are generated by the phase-locked loop

(PLL) from a single crystal oscillator or clock input.

The transmit path interpolation filter provides an upsampling

factor of 16× with an output signal bandwidth up to 4.35 MHz.

Carrier frequencies up to 65 MHz with 26 bits of frequency tuning

resolution can be generated by the direct digital synthesizer

(DDS). The transmit DAC resolution is 12 bits and can run at

sampling rates as high as 232 MSPS. Analog output scaling from

0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when

reduced output levels are required.

The 12-bit ADCs provide excellent undersampling performance,

allowing this device to typically deliver better than 10 ENOBs

with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at

rates up to 29 MHz, allowing them to process wideband signals.

The AD9878 includes a programmable ∑-∆ DAC, which can be

used to control an external component such as a variable gain

amplifier (VGA) or a voltage controlled tuner.

The AD9878 also integrates a CA port that enables a host

processor to interface with the AD832x family of programmable

gain amplifier (PGA) cable drivers or industry equivalent via

the MxFE serial port (SPORT).

The AD9878 is available in a 100-lead, LQFP package. The

AD9878 is specified over the extended industrial (−40°C to

+85°C) temperature range.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

AD9878

TABLE OF CONTENTS

Electrical Characteristics ................................................................. 4

Absolute Maximum Ratings............................................................ 7

Explanation of Test Levels ........................................................... 7

Thermal Characteristics .............................................................. 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 13

Registers 0x10 Through 0x17—Burst Parameter................... 17

Serial Interface for Register Control ............................................ 18

General Operation of the Serial Interface ............................... 18

Instruction Byte .......................................................................... 18

Serial Interface Port Pin Descriptions ..................................... 18

MSB/LSB Transfers..................................................................... 19

Notes on Serial Port Operation ................................................ 19

Theory of Operation ...................................................................... 20

Transmit Path.............................................................................. 21

Data Assembler........................................................................... 21

Transmit Timing......................................................................... 21

Interpolation Filter..................................................................... 21

Half-Band Filters (HBFs) .......................................................... 21

Cascade Integrator Comb (CIC) Filter.................................... 21

Combined Filter Response........................................................ 21

Digital Upconverter ................................................................... 22

Tx Signal Level Considerations ................................................ 22

Tx Throughput and Latency ..................................................... 23

DAC.............................................................................................. 23

Programming the AD8321/AD8323 or

AD8322/AD8327/AD8238 Cable-Driver Amplifiers............ 23

OSCIN Clock Multiplier ........................................................... 24

Clock and Oscillator Circuitry ................................................. 24

Programmable Clock Output REFCLK .................................. 24

Power-Up Sequence ................................................................... 26

Reset ............................................................................................. 26

Transmit Power-Down .............................................................. 26

∑-∆ Outputs ................................................................................ 27

Receive Path (Rx) ....................................................................... 27

IF10 and IF12 ADC Operation ................................................ 27

ADC Voltage References ........................................................... 29

Video Input ................................................................................. 29

PCB Design Considerations.......................................................... 30

Component Placement .............................................................. 30

Power Planes and Decoupling .................................................. 30

Ground Planes ............................................................................ 30

Signal Routing............................................................................. 30

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

Rev. A | Page 2 of 36

AD9878-EB Related Products

	AD9878-EB	AD9878
Description	Mixed-Signal Front End for Broadband Applications	Mixed-Signal Front End for Broadband Applications

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