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709159L7BF

Description
CABGA-100, Tray
Categorystorage    storage   
File Size339KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
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709159L7BF Overview

CABGA-100, Tray

709159L7BF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeCABGA
package instruction10 X 10 MM, 1.4 MM HEIGHT, 0.8 MM PITCH, FBGA-100
Contacts100
Manufacturer packaging codeBF100
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time7.5 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)83 MHz
I/O typeCOMMON
JESD-30 codeS-PBGA-B100
JESD-609 codee0
length10 mm
memory density73728 bit
Memory IC TypeDUAL-PORT SRAM
memory width9
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals100
word count8192 words
character code8000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8KX9
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLFBGA
Encapsulate equivalent codeBGA100,10X10,32
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height1.4 mm
Maximum standby current0.003 A
Minimum standby current4.5 V
Maximum slew rate0.4 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width10 mm
Base Number Matches1
HIGH-SPEED 16/8K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features
709169/59L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9ns (max.)
Industrial: 7.5ns (max.)
Low-power operation
– IDT709169/59L
Active: 925mW (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the
FT/PIPE
pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
FT/PIPE
L
S
T OR
R F
A D
P E
E D
T N
E E
S
L M
N
O M
S
IG
B
S
O
E
O EC
D
R EW
T N
O
N
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time,100MHz operation in Pipelined output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
R/W
R
OE
R
1
0
0/1
1
0
0/1
CE
0R
CE
1R
0/1
1
0
0
1
0/1
FT/PIPE
R
I/O
0L
- I/O
8L
I/O
0R
- I/O
8R
I/O
Control
I/O
Control
A
13L(1)
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
13R(1)
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
5653 drw 01
NOTE:
1. A
13
is a NC for IDT709159.
APRIL 2019
1
DSC-5653/4
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