®
EMIF02-MIC02F2
IPAD™
2 LINES EMI FILTER
INCLUDING ESD PROTECTION
MAIN PRODUCT CHARACTERISTICS:
Where EMI filtering in ESD sensitive equipment is
required:
■
Mobile phones and communication systems
■
Computers, printers and MCU Boards
DESCRIPTION
The EMIF02-MIC02 is a highly integrated devices
designed to suppress EMI/RFI noise in all systems
subjected to electromagnetic interferences. The
EMIF02 flip chip packaging means the package
size is equal to the die size.
This filter includes an ESD protection circuitry
which prevents the device from destruction when
subjected to ESD surges up 15kV.
BENEFITS
■
EMI symmetrical (I/O) low-pass filter
■
High efficiency in EMI filtering
■
Lead free package
■
Very low PCB space consuming:
1.07mm x 1.57mm
■
Very thin package: 0.65 mm
■
High efficiency in ESD suppression
■
High reliability offered by monolithic integration
■
High reducing of parasitic elements through
integration & wafer level packaging.
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2
Level 4 on input pins 15kV (air discharge)
8kV (contact discharge)
Level 1 on output pins 2kV
2kV
(air discharge)
(contact discharge)
Flip-Chip
(6 Bumps)
Table 1: Order Code
Part Number
EMIF02-MIC02F2
Marking
FJ
Figure 1: Pin Configuration (Ball side)
3
I2
O2
2
GND
GND
1
I1
O1
A
B
Figure 2: Basic Cell Configuration
Low-pass Filter
Input
Output
Ri/o = 470
Ω
Cline = 16pF
GND
TM:
IPAD is a trademark of STMicroelectronics.
GND
GND
October 2004
REV. 1
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EMIF02-MIC02F2
Table 2: Absolute Ratings
(limiting values)
Symbol
T
j
T
op
T
stg
Parameter and test conditions
Maximum junction temperature
Operating temperature range
Storage temperature range
Value
125
- 40 to + 85
- 55 to + 150
Unit
°C
°C
°C
Table 3: Electrical Characteristics
(T
amb
= 25°C)
Symbol
V
BR
I
RM
V
RM
V
CL
R
d
I
PP
R
I/O
C
line
Symbol
V
BR
I
RM
R
I/O
C
line
@ 0V
I
R
= 1 mA
V
RM
= 12V per line
423
470
16
Parameter
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Dynamic impedance
Peak pulse current
Series resistance between Input &
Output
Input capacitance per line
Test conditions
Min.
14
Typ.
16
500
517
Max.
Unit
V
nA
Ω
pF
I
PP
V
CL
V
BR
V
RM
I
R
I
RM
I
RM
I
R
V
RM
V
BR
V
CL
V
I
I
PP
Figure 3: S21 (dB) attenuation measurement
and Aplac simulation
- 10.00
dB
- 15.00
- 20.00
- 25.00
- 30.00
- 35.00
Measurement
Figure 4: Analog crosstalk measurements
-20.00
dB
-
-30.00
-
-40.00
I2/O1
-
-50.00
-
-60.00
- 40.00
- 45.00
Simulation
-
-70.00
- 50.00
1.0M
3.0M
10.0M
30.0M
100.0M
f/Hz
300.0M
1.0G
3.0G
-
-80.00
1.0M
3.0M
10.0M
30.0M
100.0M
f/Hz
300.0M
1.0G
3.0G
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EMIF02-MIC02F2
Figure 5: Digital crosstalk measurement
Figure 6: ESD response to IEC61000-4-2
(+15kV air discharge) on one input V(in) and on
one output (Vout)
Figure 7: ESD response to IEC61000-4-2
(+15kV air discharge) on one input V(in) and on
one output (Vout)
Figure 8: Line capacitance versus applied
voltage
C(pF)
20
18
16
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
9
10
11
12
V
R
(V)
F=1MHz
V
osc
=30mV
RMS
T
j
=25°C
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EMIF02-MIC02F2
Figure 9: Aplac model
R_470R
O1
I1
gnd
Cox
MODEL = D01-int
MODEL = D01-ext
Cox
50pH
Rsubump
MODEL = D01-gnd
gnd
50pH
Rsubump
50m
50m
Rsubump
MODEL = D01-ext
Cox
MODEL = D01-int
Rsubump
Lgnd
Cgnd
Cgnd
Rgnd
O2
Lgnd
Cox
Rgnd
I2
R_470R
Figure 10: Aplac parameters
Model D01-ext
BV = 7
CJO = Cz_ext
IBV = 1u
IKF = 1000
IS = 10f
ISR = 100p
N=1
M = 0.3333
RS = Rs_ext
VJ = 0.6
TT = 50n
Model D01-int
BV = 7
CJO = Cz_int
IBV = 1u
IKF = 1000
IS = 10f
ISR = 100p
N=1
M = 0.3333
RS = Rs_int
VJ = 0.6
TT = 50n
Model D01-gnd
BV = 7
CJO = Cz_gnd
IBV = 1u
IKF = 1000
IS = 10f
ISR = 100p
N=1
M = 0.3333
RS = Rs_gnd
VJ = 0.6
TT = 50n
Ls 400pH
Rs 100m
R_470R 482.6
Cz_ext 8.73pF
Rs_ext 850m
Cz_int 2.9pF
Rs_int 850m
Cz_gnd 215.61pF
Rs_gnd 470m
Rgnd 10m
Lgnd 48pH
Cgnd 0.15pF
Cox 3.05pF
Rsubump 200m
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EMIF02-MIC02F2
Figure 11: Ordering Information Scheme
EMIF
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
x = 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
= 3: Leadfree Pitch = 400µm, Bump = 250µm
yy
-
xxx zz
Fx
Figure 12: FLIP-CHIP Package Mechanical Data
500µm ± 50
315µm ± 50
650µm ± 65
500µm ± 50
1.07mm ± 50µm
Figure 13: Foot print recommendations
1.57mm ± 50µm
Figure 14: Marking
Copper pad Diameter :
250µm recommended , 300µm max
Solder stencil opening : 330µm
Dot, ST logo
xx = marking
z = packaging
location
yww = datecode
(y = year
ww = week)
365
240
365
E
Solder mask opening recommendation :
340µm min for 300µm copper pad diameter
x x z
y ww
40
220
All dimensions in µm
5/7
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