CP80S54/56
EPROM/ROM-Based 8-Bit Microcontroller Series
Devices Included in this Data Sheet:
‧
CP80S54E/S56E
: EPROM devices
‧
CP80S54/S56
: Mask ROM devices
FEATURES
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Only 42 single word instructions
All instructions are single cycle except for program branches which are two-cycle
13-bit wide instructions
All ROM/EPROM area GOTO instruction
All ROM/EPROM area subroutine CALL instruction
8-bit wide data path
5-level deep hardware stack
Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
Device
CP80S54/S54E
CP80S56/S56E
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Pins #
18
18
I/O #
16
16
EPROM/ROM (Byte)
512
1K
RAM (Byte)
49
49
‧
Direct, indirect addressing modes for data accessing
8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
Internal Power-on Reset (POR)
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
Two I/O ports IOA and IOB with independent direction control (maximum 16 I/O pins)
Soft-ware I/O pull-high/pull-down or open-drain control
One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change
Wake-up from SLEEP by INT pin or Port B input change
Power saving SLEEP mode
Built-in 8MHz, 4MHz, 1MHz, and 455KHz internal RC oscillator
Programmable Code Protection
Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- XT: Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
- ERIC: External Resistor/Internal Capacitor Oscillator
Wide-operating voltage range:
- EPROM : 2.3V to 5.5V
- ROM : 2.3V to 5.5V
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Rev0.1 Nov 30, 2005
P.1/
CP
80S54/S56
CP80S54/56
GENERAL DESCRIPTION
The
CP80S54/S56
series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit CMOS
microcontrollers. It employs a RISC architecture with only 42 instructions. All instructions are single cycle except
for program branches which take two cycles. The easy to use and easy to remember instruction set reduces
development time significantly.
The
CP80S54/S56
series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer
(PWRT), Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O
pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter,
Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are three oscillator
configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator.
The
CP80S54/S54E
address 512×13 of program memory, and the
CP80S56/S56E
address 1K×13 of program
memory.
The
CP80S54/S56
can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
Oscillator
Circuit
5-level
STACK
Watchdog
Timer
Program
Counter
FSR
SRAM
ALU
EPROM
/ ROM
Instruction
Decoder
PORTA
PORTB
Interrupt
Control
Timer0
Accumulator
Rev0.1 Nov 30, 2005
P.2/CP80S54/S56
CP80S54/56
PIN CONNECTION
PDIP, SOP
IOA2
IOA3
IOA4/T0CKI
IOA5/RSTB
Vss
IOB0/INT
IOB1
IOB2
IOB3
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
IOA1
IOA0
IOA7/OSCI
IOA6/OSCO
Vdd
IOB7
IOB6
IOB5
IOB4
SSOP
IOA2
IOA3
IOA4/T0CKI
IOA5/RSTB
Vss
Vss
IOB0/INT
IOB1
IOB2
IOB3
1
2
3
4
5
6
7
8
9
10
20
19
18
IOA1
IOA0
IOA7/OSCI
IOA6/OSCO
Vdd
Vdd
IOB7
IOB6
IOB5
IOB4
CP8054S
CP8054SE
CP8056S
CP8056SE
CP8054S
CP8054SE
CP8056S
CP8056SE
17
16
15
14
13
12
11
PIN DESCRIPTIONS
Description
IOA0 ~ IOA7 as bi-direction I/O port, and IOA5 is an input only pin.
Bi-direction I/O pin with system wake-up function / External interrupt input
Bi-direction I/O port with system wake-up function
Clock input to Timer0. Must be tied to Vss or Vdd, if not in use, to reduce current
T0CKI
I
consumption
RSTB
I
System clear (RESET) input. This pin is an active low RESET to the device.
X’tal type: Oscillator crystal input
OSCI
I
RC type: Clock input of RC oscillator
X’tal type: Oscillator crystal output.
OSCO
O
RC mode: Outputs with the instruction cycle rate
Vdd
-
Positive supply
Vss
-
Ground
Legend: I=input, O=output, I/O=input/output
Name
IOA0 ~ IOA7
IOB0/INT
IOB1 ~ IOB7
I/O
I/O
I/O
I/O
Rev0.1 Nov 30, 2005
P.3/CP80S54/S56
CP80S54/56
1.0 MEMORY ORGANIZATION
CP80S54/S56
memory is organized into program memory and data memory.
1.1 Program Memory Organization
The
CP80S54/S54E
have a 9-bit Program Counter (PC) capable of addressing a 512×13 program memory space.
The
CP80S56/S56E
have a 10-bit Program Counter capable of addressing a 1K×13 program memory space.
The RESET vector for the
CP80S54/S54E
is at 1FFh. The RESET vector for the
CP80S56/S56E
is at 3FFh.
The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h.
CP80S54/S56
supports all ROM/EPROM area CALL/GOTO instructions without page.
FIGURE 1.1: Program Memory Map and STACK
PC<9:0>
PC<8:0>
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
3FFh
Reset Vector
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
1FFh
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
CP80S54/S54E
Reset Vector
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
CP80S56/S56E
Rev0.1 Nov 30, 2005
P.4/CP80S54/S56
CP80S54/56
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the
operation of the device.
TABLE 1.1: Registers File Map for CP8054/56 Series
Address
Description
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h ~ 3Fh
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
General Purpose Register
PCON
WUCON
PCHBUF
PDCON
ODCON
PHCON
INTEN
INTFLAG
General Purpose Registers
N/A
OPTION
05h
06h
IOSTA
IOSTB
TABLE 1.2: The Registers Controlled by OPTION or IOST Instructions
Address
Name
B7
B6
B5
B4
B3
N/A (w)
05h (w)
06h (w)
OPTION
IOSTA
IOSTB
-
INTEDG
T0CS
B2
B1
PS1
B0
PS0
T0SE
PSA
PS2
Port A I/O Control Register
Port B I/O Control Register
TABLE 1.3: Operational Registers Map
Address
Name
B7
B6
00h (r/w)
01h (r/w)
02h (r/w)
03h (r/w)
04h (r/w)
05h (r/w)
06h (r/w)
07h (r/w)
08h (r/w)
09h (r/w)
0Ah (r/w)
0Bh (r/w)
0Ch (r/w)
0Dh (r/w)
0Eh (r/w)
0Fh (r/w)
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
SRAM
PCON
WUCON
PCHBUF
(2)
PDCON
ODCON
PHCON
INTEN
INTFLAG
B5
B4
B3
B2
B1
B0
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
Low order 8 bits of PC
GP2
GP1
GP0
TO
PD
Z
DC
C
*
*
Indirect data memory address pointer
IOA7
IOA6
IOA5
IOA4
IOA3
IOA2
IOA1
IOA0
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
IOB1
IOB0
General Purpose Register
WDTE
EIS
LVDTE
ROC
-
-
-
-
WUB7
WUB6
WUB5
WUB4
WUB3
WUB2
WUB1
WUB0
-
-
-
-
-
2 MSBs Buffer of PC
/PDB3
/PDB2
/PDB1
/PDB0
/PDA3
/PDA2
/PDA1
/PDA0
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
/PHB7
/PHB6
/PHB5
/PHB4
/PHB3
/PHB2
/PHB1
/PHB0
GIE
-
-
-
-
INTIE
PBIE
T0IE
-
-
-
-
-
INTIF
PBIF
T0IF
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’
Note 1 : There is only 1 bit in
CP80S54/S54E.
And there are 2 bits in
CP80S56/S56E.
Rev0.1 Nov 30, 2005
P.5/CP80S54/S56
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