5962-89839012A datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> 5962-89839012A

5962-89839012A: DescriptionEE PLD, 55ns, CMOS, CQCC20, 0.350 X 0.350 INCH, CERAMIC, LCC-20; CategoryProgrammable logic devices Programmable logic; File Size837KB，27 Pages; ManufacturerAMD; Websitehttp://www.amd.com

Download Datasheet Parametric Compare View All

5962-89839012A Overview

EE PLD, 55ns, CMOS, CQCC20, 0.350 X 0.350 INCH, CERAMIC, LCC-20

5962-89839012A Parametric

Parameter Name	Attribute value
Maker	AMD
Parts packaging code	QLCC
package instruction	QCCN,
Contacts	20
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Other features	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET
maximum clock frequency	28.6 MHz
JESD-30 code	S-CQCC-N20
JESD-609 code	e0
length	8.89 mm
Dedicated input times	8
Number of I/O lines	8
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Package shape	SQUARE
Package form	CHIP CARRIER
Programmable logic type	EE PLD
propagation delay	55 ns
Certification status	Not Qualified
Maximum seat height	2.54 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	QUAD
width	8.89 mm
Base Number Matches	1

Preview

Download Datasheet

View All

5962-89839012A Related Products

	5962-89839012A	5962-8983902RA	5962-89839022A	5962-89839032A	5962-8983901RA	5962-8983903RA	PALCE16V8H-10E5/B2A	PALCE16V8H-10E5/BRA	PALCE16V8H-15E5/B2A	PALCE16V8H-15E5/BRA
Description	EE PLD, 55ns, CMOS, CQCC20, 0.350 X 0.350 INCH, CERAMIC, LCC-20	EE PLD, 20ns, CMOS, CDIP20, 0.250 X 1.166 INCH, CERAMIC, DIP-20	EE PLD, 20ns, CMOS, CQCC20, 0.350 X 0.350 INCH, CERAMIC, LCC-20	EE PLD, 15ns, CMOS, CQCC20, 0.350 X 0.350 INCH, CERAMIC, LCC-20	EE PLD, 55ns, CMOS, CDIP20, 0.250 X 1.166 INCH, CERAMIC, DIP-20	EE PLD, 15ns, CMOS, CDIP20, 0.250 X 1.166 INCH, CERAMIC, DIP-20	EE PLD, 10ns, PAL-Type, CMOS, CQCC20, CERAMIC, LCC-20	EE PLD, 10ns, PAL-Type, CMOS, CDIP20, CERAMIC, DIP-20	EE PLD, 15ns, PAL-Type, CMOS, CQCC20, CERAMIC, LCC-20	EE PLD, 15ns, PAL-Type, CMOS, CDIP20, CERAMIC, DIP-20
Parts packaging code	QLCC	DIP	QLCC	QLCC	DIP	DIP	QLCC	DIP	QLCC	DIP
package instruction	QCCN,	DIP,	QCCN,	QCCN,	DIP,	DIP,	QCCN, LCC20,.35SQ	DIP, DIP20,.3	QCCN, LCC20,.35SQ	DIP, DIP20,.3
Contacts	20	20	20	20	20	20	20	20	20	20
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
Other features	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET
maximum clock frequency	28.6 MHz	33.3 MHz	33.3 MHz	41.6 MHz	28.6 MHz	41.6 MHz	58.5 MHz	58.5 MHz	41.6 MHz	41.6 MHz
JESD-30 code	S-CQCC-N20	R-GDIP-T20	S-CQCC-N20	S-CQCC-N20	R-GDIP-T20	R-GDIP-T20	S-CQCC-N20	R-GDIP-T20	S-CQCC-N20	R-GDIP-T20
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0	e0	e0
length	8.89 mm	24.257 mm	8.89 mm	8.89 mm	24.257 mm	24.257 mm	8.89 mm	24.257 mm	8.89 mm	24.257 mm
Dedicated input times	8	8	8	8	8	8	8	8	8	8
Number of I/O lines	8	8	8	8	8	8	8	8	8	8
Number of terminals	20	20	20	20	20	20	20	20	20	20
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
organize	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED
encapsulated code	QCCN	DIP	QCCN	QCCN	DIP	DIP	QCCN	DIP	QCCN	DIP
Package shape	SQUARE	RECTANGULAR	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE	CHIP CARRIER	CHIP CARRIER	IN-LINE	IN-LINE	CHIP CARRIER	IN-LINE	CHIP CARRIER	IN-LINE
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	55 ns	20 ns	20 ns	15 ns	55 ns	15 ns	10 ns	10 ns	15 ns	15 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.54 mm	5.08 mm	2.54 mm	2.54 mm	5.08 mm	5.08 mm	2.54 mm	5.08 mm	2.54 mm	5.08 mm
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	YES	YES	NO	NO	YES	NO	YES	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD	THROUGH-HOLE	NO LEAD	NO LEAD	THROUGH-HOLE	THROUGH-HOLE	NO LEAD	THROUGH-HOLE	NO LEAD	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm	2.54 mm	1.27 mm	2.54 mm
Terminal location	QUAD	DUAL	QUAD	QUAD	DUAL	DUAL	QUAD	DUAL	QUAD	DUAL
width	8.89 mm	7.62 mm	8.89 mm	8.89 mm	7.62 mm	7.62 mm	8.89 mm	7.62 mm	8.89 mm	7.62 mm
Base Number Matches	1	1	1	1	1	1	1	1	1	1

Recommended Resources

Voltage regulation and stabilization circuit diagram using power transformer for compensation

Overvoltage protection circuit diagram composed of fuse and thyristor

Broadband Noise Amplifier

Building block reference voltage source circuit diagram 1

Ultra-low drift ECG signal amplifier circuit

555 flowerpot water shortage informer circuit

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components