IDT70V631S12PRF9 datasheet, PDF

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IDT70V631S12PRF9: DescriptionDual-Port SRAM, 256KX18, 12ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128; Categorystorage storage; File Size201KB，23 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT70V631S12PRF9 Overview

Dual-Port SRAM, 256KX18, 12ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128

IDT70V631S12PRF9 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
Contacts	128
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	12 ns
JESD-30 code	R-PQFP-G128
JESD-609 code	e0
length	20 mm
memory density	4718592 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	128
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX18
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

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HIGH-SPEED 3.3V 256K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

◆

IDT70V631S

Features

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 10/12/15ns (max.)

– Industrial: 12ns (max.)

Dual chip enables allow for depth expansion without

external logic

IDT70V631 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

◆

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Supports JTAG features compliant to IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

128-pin TQFP package.

LVTTL-compatible, single 3.3V (±150mV) power supply for

core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 128-pin Thin Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Functional Block Diagram

0 R

1 R

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

256K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

17L

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

17R

R/W

BUSY

SEM

INT

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

0 R

1 R

R/W

BUSY

M/S

SEM

INT

TDI

TDO

JTAG

TMS

TCK

TRST

5622 drw 01

NOTES:

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

OCTOBER 2003

DSC-5622/5

IDT70V631S12PRF9 Related Products

	IDT70V631S12PRF9	IDT70V631S15PRFG	IDT70V631S15PRF9	IDT70V631S15BFG	IDT70V631S12PRFG	IDT70V631S12BFG	WBDDSS8-A-01-1580-D-	IDT70V631S10PRF9	IDT70V631S12BCGI	IDT70V631S12BCG
Description	Dual-Port SRAM, 256KX18, 12ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128	Dual-Port SRAM, 256KX18, 15ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128	Dual-Port SRAM, 256KX18, 15ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128	Dual-Port SRAM, 256KX18, 15ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208	Dual-Port SRAM, 256KX18, 12ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128	Dual-Port SRAM, 256KX18, 12ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208	Array/Network Resistor, Isolated, 0.1W, 158ohm, 100V, 0.5% +/-Tol, -100,100ppm/Cel, 1408,	Dual-Port SRAM, 256KX18, 10ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128	Dual-Port SRAM, 256KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256	Dual-Port SRAM, 256KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	EAR99	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Number of terminals	128	128	128	208	128	208	16	128	256	256
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	150 °C	70 °C	85 °C	70 °C
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	SMT	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Is it lead-free?	Contains lead	Lead free	Contains lead	Lead free	Lead free	Lead free	-	Contains lead	Lead free	Lead free
Is it Rohs certified?	incompatible	conform to	incompatible	conform to	conform to	conform to	-	incompatible	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	-	-
Parts packaging code	QFP	QFP	QFP	BGA	QFP	BGA	-	QFP	BGA	BGA
package instruction	14 X 20 MM, 1.40 MM HEIGHT, TQFP-128	LFQFP,	14 X 20 MM, 1.40 MM HEIGHT, TQFP-128	LFBGA,	LFQFP,	LFBGA,	-	14 X 20 MM, 1.40 MM HEIGHT, TQFP-128	LBGA,	LBGA,
Contacts	128	128	128	208	128	208	-	128	256	256
Maximum access time	12 ns	15 ns	15 ns	15 ns	12 ns	12 ns	-	10 ns	12 ns	12 ns
JESD-30 code	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128	S-PBGA-B208	R-PQFP-G128	S-PBGA-B208	-	R-PQFP-G128	S-PBGA-B256	S-PBGA-B256
JESD-609 code	e0	e3	e0	e1	e3	e1	-	e0	e1	e1
length	20 mm	20 mm	20 mm	15 mm	20 mm	15 mm	-	20 mm	17 mm	17 mm
memory density	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit	-	4718592 bit	4718592 bit	4718592 bit
Memory IC Type	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	-	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
memory width	18	18	18	18	18	18	-	18	18	18
Humidity sensitivity level	3	3	3	3	3	3	-	3	3	3
Number of functions	1	1	1	1	1	1	-	1	1	1
word count	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	-	262144 words	262144 words	262144 words
character code	256000	256000	256000	256000	256000	256000	-	256000	256000	256000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
organize	256KX18	256KX18	256KX18	256KX18	256KX18	256KX18	-	256KX18	256KX18	256KX18
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	LFQFP	LFBGA	LFQFP	LFBGA	-	LFQFP	LBGA	LBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE	-	RECTANGULAR	SQUARE	SQUARE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	-	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	240	260	240	260	260	260	-	240	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.7 mm	1.6 mm	1.7 mm	-	1.6 mm	1.7 mm	1.7 mm
Maximum supply voltage (Vsup)	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	-	3.45 V	3.45 V	3.45 V
Minimum supply voltage (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	-	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	-	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	-	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	-	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	TIN LEAD	MATTE TIN	TIN LEAD	Tin/Silver/Copper (Sn/Ag/Cu)	MATTE TIN	Tin/Silver/Copper (Sn/Ag/Cu)	-	TIN LEAD	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	GULL WING	GULL WING	GULL WING	BALL	GULL WING	BALL	-	GULL WING	BALL	BALL
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.8 mm	0.5 mm	0.8 mm	-	0.5 mm	1 mm	1 mm
Terminal location	QUAD	QUAD	QUAD	BOTTOM	QUAD	BOTTOM	-	QUAD	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	20	30	20	30	30	30	-	20	30	30
width	14 mm	14 mm	14 mm	15 mm	14 mm	15 mm	-	14 mm	17 mm	17 mm
Base Number Matches	1	1	1	1	1	1	-	1	1	1

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