FemtoClock™ SAS/SATA Clock Generator
843751
DATA SHEET
General Description
The 843751 is a low jitter, high performance clock generator. The
843751 is designed for use in the SAS-2 interconnect and the three
transport protocols that use the SAS-2 interconnect: Serial SCSI
Protocol (SSP), Serial ATA Tunneled Protocol (STP), and Serial
Management Protocol (SMP). The 843751 has excellent (<1ps)
RMS phase jitter, over the SAS defined integration range. The
843751 uses an external, 25MHz, parallel resonant crystal to
generate 75MHz. This silicon based approach provides excellent
frequency stability and reliability. The 843751 features up, down, and
center spread spectrum (SSC) clocking techniques. The up, down
and center SSC will be required in the SAS-2 applications that have
three clock trees in the HBA and expander ASICs.
Features
•
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Designed for use in SAS, SAS-2 systems
Up, down and center Spread Spectrum Clocking (SSC)
One differential 3.3V or 2.5V LVPECL output pair
Output frequency: 75MHz
RMS phase jitter @ 75MHz, (900kHz – 7.5MHz):
0.734ps (typical) @ 3.3V
3.3V or 2.5V operating supply modes
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Functional replacement part: 843002AYLF
Applications
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SAS/SATA Host Bus Adapters
SATA Port Multipliers
SAS I/O Controllers
TapeDrive and HDD Array Controllers
SAS Edge and Fanout Expanders
HDDs and TapeDrives
Disk Storage Enterprise
Block Diagram
XTAL_IN
XTAL_OUT
SSC_SEL[1:0]
Pulldown
25MHz
75MHz
Pin Assignment
FemtoClock™
PLL
Q
nQ
OSC
843751
8-Lead SOIC, 150 Mil
3.90mm x 4.90mm x 1.375mm package body
M Package
Top View
843751 REVISION B 08.21.15
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©2015 Integrated Device Technology, Inc.
843751 Data Sheet
FEMTOCLOCK™ SAS/SATA CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1,
2
3,
4
5
6, 7
8
Name
XTAL_OUT,
XTAL_IN
SSC_SEL0,
SSC_SEL1
V
CC
Q, nQ
V
EE
Input
Input
Power
Output
Power
Pulldown
Type
Description
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
Power supply pin.
Differential clock outputs. LVPECL interface levels.
Negative supply pin.
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Function Tables
Table 3. SSC_SEL[1:0] Function Table
Inputs
SSC_SEL1
0 (default)
0
1
1
SSC_SEL0
0 (default)
1
0
1
Mode
SSC Off
0.5% Down-spread
0.5% Up-spread
0.5% Center-spread
843751 REVISION B 08.21.15
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©2015 Integrated Device Technology, Inc.
843751 Data Sheet
FEMTOCLOCK™ SAS/SATA CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
96°C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
77
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
75
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
Input Low Voltage
Input High Current
Input Low Current
SSC_SEL[0:1]
SSC_SEL[0:1]
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= V
IN
= 3.465V or 2.5V
V
CC
= 3.465V or 2.5V, V
IN
= 0V
-5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
843751 REVISION B 08.21.15
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©2015 Integrated Device Technology, Inc.
843751 Data Sheet
FEMTOCLOCK™ SAS/SATA CLOCK GENERATOR
Table 4D. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
0.9
Units
V
V
V
NOTE 1: Output termination with 50 to V
CC
– 2V.
Table 4E. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.4
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.5
0.9
Units
V
V
V
NOTE 1: Output termination with 50 to V
CC
– 2V.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency; NOTE 1
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
pF
843751 REVISION B 08.21.15
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©2015 Integrated Device Technology, Inc.
843751 Data Sheet
FEMTOCLOCK™ SAS/SATA CLOCK GENERATOR
AC Electrical Characteristics
Table 6A. AC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
f
OUT
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter
(Random); NOTE 1
Output Rise/Fall Time
Output Duty Cycle
75MHz,
Integration Range: 900kHz – 7.5MHz
20% to 80%
325
48
Test Conditions
Minimum
Typical
75
0.734
575
52
Maximum
Units
MHz
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Refer to the Phase Noise plot.
Table 6B. AC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
f
OUT
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter
(Random); NOTE 1
Output Rise/Fall Time
Output Duty Cycle
75MHz,
Integration Range: 900kHz – 7.5MHz
20% to 80%
325
48
Test Conditions
Minimum
Typical
75
0.755
575
52
Maximum
Units
MHz
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Refer to the Phase Noise plot.
843751 REVISION B 08.21.15
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©2015 Integrated Device Technology, Inc.
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