80312 datasheet, PDF - EEWORLD Datasheet

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80312: DescriptionMicroprocessor Circuit, CMOS, PBGA540, PLASTIC, BGA-540; CategoryThe embedded processor and controller Microcontrollers and processors; File Size862KB，52 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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80312 Overview

Microprocessor Circuit, CMOS, PBGA540, PLASTIC, BGA-540

80312 Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	BGA
package instruction	BGA,
Contacts	540
Reach Compliance Code	unknown
JESD-30 code	S-PBGA-B540
length	42.5 mm
Number of terminals	540
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	42.5 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR CIRCUIT
Base Number Matches	1

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Intel

80312 I/O Companion Chip

Datasheet

Product Features

Core Interface Unit

—100 MHz Request Bus

—Data Bus shared with Intel

80200

processor and SDRAM

—4-Entry Request Buffer

PCI-to-PCI Bridge Unit

—Primary and Secondary 66 MHz/64-bit

PCI Interfaces

—Eight Delayed Read/Write Buffers and

Two Posting Buffers

—Six Secondary PCI Output Clocks

—Forwards Memory, I/O, Configuration

Commands from PCI Bus to PCI Bus

—Complies with

PCI Local Bus

Specification,

Revision 2.2

—Universal (5 V and 3.3 V) PCI Signaling

Environment

Memory Controller

—100 MHz SDRAM Support

—512 Mbytes of 64-Bit SDRAM

—Four SDRAM Output Clocks

—ECC Single-Bit error correction,

Double-Bit error detection

—Two Independent Banks for SRAM / ROM

/ Flash (8 Mbyte/Bank; 8-Bit)

Two Address Translation Units

—Connects Internal Bus to 64-bit PCI Buses

—I/O Address Translation Support

—Direct Outbound Addressing Support

DMA Controller

— Three Independent Channels

— PCI Memory Controller Interface

— 64-Bit Internal and PCI Bus Addressing

— Independent Interface to 66 MHz/64-bit

Primary and Secondary PCI Buses

— 528 Mbyte/sec Burst Transfers to PCI and

SDRAM Memory

— Direct Addressing to/from PCI Buses

— Unaligned Transfers Supported in

Hardware

—Two Channels Dedicated to Primary PCI

Bus

—One Channel Dedicated to Secondary PCI

Bus

I C Bus Interface Unit

— Serial Bus

— Master/Slave Capabilities

— System Management Functions

Secondary PCI Arbitration Unit

— Supports Six Secondary PCI Devices

— Multi-priority Arbitration Algorithm

Private PCI Device Support

540 Ball - Plastic Ball Grid Array

(H-PBGA)

O* Messaging Unit

Application Accelerator

— Built-in hardware XOR engine

— 512 or 1 Kbyte Queue

Performance Monitoring

— Ninety-eight Events Monitored On-Chip

Eight General Purpose I/O Pins

Order Number: 273425-008

August 10, 2001

Intel

80312 I/O Companion Chip

Contents

1.1

1.2

2.0

Terminology........................................................................................................... 5

Additional Information Sources ............................................................................. 5

Functional Overview........................................................................................................... 6

2.1

Key Functional Units ............................................................................................. 8

2.1.1 PCI-to-PCI Bridge Unit ............................................................................. 8

2.1.2 Private PCI Device Support...................................................................... 8

2.1.3 DMA Controller......................................................................................... 8

2.1.4 Address Translation Unit .......................................................................... 8

2.1.5 Messaging Unit......................................................................................... 8

2.1.6 Memory Controller Unit ............................................................................ 9

2.1.7 I

C Bus Interface Unit............................................................................... 9

2.1.8 Secondary PCI Arbitration Unit ................................................................ 9

2.1.9 Application Accelerator Unit ..................................................................... 9

2.1.10 Performance Monitor Unit ........................................................................ 9

2.1.11 Core Interface Unit ................................................................................... 9

Intel

80200 Processor Features ........................................................................ 10

2.2

3.0

Package Information ........................................................................................................11

3.1

Package Introduction........................................................................................... 11

3.1.1 Functional Signal Definitions ..................................................................11

3.1.2 540-Lead H-PBGA Package ..................................................................23

Package Thermal Specifications .........................................................................35

3.2.1 Thermal Specifications ........................................................................... 35

3.2.2 Thermal Analysis .................................................................................... 36

Heat Sink Information ..........................................................................................37

3.3.1 Socket Information ................................................................................. 37

3.3.2 Socket-Header Vendor........................................................................... 37

3.3.3 Burn-in Socket Vendor ........................................................................... 37

3.3.4 Shipping Tray Vendor............................................................................. 38

3.3.5 Logic Analyzer Interposer Vendor .......................................................... 38

3.2

3.3

4.0

Electrical Specifications.................................................................................................... 39

4.1

4.2

4.3

4.4

4.5

Absolute Maximum Ratings................................................................................. 39

CC5REF

Pin Requirements (V

DIFF

)..................................................................... 40

CCPLL

Pin Requirements ................................................................................... 41

Targeted DC Specifications................................................................................. 42

Targeted AC Specifications................................................................................. 44

4.5.1 Clock Signal Timings ..............................................................................44

4.5.2 PCI Interface Signal Timings ..................................................................45

4.5.3 Miscellaneous Signal Interface Timings ................................................. 46

4.5.4 SDRAM/Flash Interface Signal Timings ................................................. 46

4.5.5 Intel

80200 Processor Signal Timings .................................................. 47

4.5.6 Boundary Scan Test Signal Timings ...................................................... 48

4.5.7 I

C Interface Signal Timings................................................................... 48

AC Timing Waveforms ........................................................................................ 49

AC Test Conditions ............................................................................................. 51

4.6

4.7

5.0

Device Identification on Reset..........................................................................................52

Datasheet

Intel

80312 I/O Companion Chip

Figures

Intel

80310 I/O Processor Chipset System Block Diagram................................. 6

Intel

80312 I/O Companion Chip Block Diagram ................................................ 7

Intel

80200 Processor Block Diagram ............................................................... 10

540-Lead H-PBGA Package Diagram (Top and Side View) ............................... 23

540-Lead H-PBGA Package Diagram (Bottom View) ......................................... 24

Thermocouple Attachment - (A) No Heatsink / (B) With Heatsink ...................... 35

CC5REF

Current-Limiting Resistor...................................................................... 40

CCPLL

Lowpass Filter ........................................................................................ 41

P_CLK, TCK, DCLKIN, DCLKOUT Waveform .................................................... 49

Output Delay Waveform .............................................................................. 49

Output Float Waveform................................................................................ 49

and T

Input Setup and Hold Waveform ...................................................... 50

C Interface Signal Timings................................................................................ 50

AC Test Load (all signals except SDRAM and Flash signals) ............................ 51

Tables

Related Documentation......................................................................................... 5

Pin Description Nomenclature............................................................................. 12

Intel

80200 Processor Bus Interface Signals .................................................... 13

Memory Controller Signals .................................................................................. 14

Primary PCI Bus Signals ..................................................................................... 17

Secondary PCI Bus Signals ................................................................................ 19

Miscellaneous Signals......................................................................................... 21

540 L H-PBGA - Ballpad Order ........................................................................... 25

540 L H-PBGA - Signal Name Order .................................................................. 30

540-Lead H-PBGA Package Thermal Characteristics ........................................ 36

Heat Sink Vendors and Contacts ........................................................................ 37

Socket-Header Vendor........................................................................................ 37

Burn-in Socket Vendor ........................................................................................ 37

Shipping Tray Vendor ......................................................................................... 38

Logic Analyzer Interposer Vendor ....................................................................... 38

Operating Conditions .......................................................................................... 39

DIFF

Specification for Dual Power Supply Requirements (3.3 V, 5 V)............... 40

DC Characteristics .............................................................................................. 42

Characteristics .............................................................................................. 43

Clock Timings...................................................................................................... 44

PCI Signal Timings.............................................................................................. 45

Miscellaneous Signal Timings ............................................................................. 46

SDRAM / Flash Signal Timings ........................................................................... 46

Core Signal Timings ............................................................................................ 47

Boundary Scan Test Signal Timings ................................................................... 48

C Interface Signal Timings................................................................................ 48

Measure Condition Parameters .......................................................................... 50

Device ID Registers ............................................................................................ 52

Datasheet

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