74LV125PW-T datasheet, PDF - EEWORLD Datasheet

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74LV125PW-T: DescriptionLV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14; Categorylogic logic; File Size89KB，15 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LV125PW-T Overview

LV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14

74LV125PW-T Parametric

Parameter Name	Attribute value
Source Url Status Check Date	2013-06-14 00:00:00
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	TSSOP
package instruction	4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14
Contacts	14
Reach Compliance Code	unknown
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
Humidity sensitivity level	1
Number of digits	1
Number of functions	4
Number of ports	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	31 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm
Base Number Matches	1

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74LV125

Quad buffer/line driver; 3-state

Rev. 03 — 7 April 2009

Product data sheet

1. General description

The 74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible

with 74HC125 and 74HCT125.

The 74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The

3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE

causes the outputs to assume a high-impedance OFF-state.

2. Features

Wide operating voltage: 1.0 V to 5.5 V

Optimized for low voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25

°C

Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

= 25

°C

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range

74LV125N

74LV125D

74LV125DB

74LV125PW

−40 °C

to +125

°C

−40 °C

to +125

°C

−40 °C

to +125

°C

−40 °C

to +125

°C

Name

DIP14

SO14

SSOP14

TSSOP14

Description

plastic dual in-line package; 14 leads (300 mil)

plastic small outline package; 14 leads;

body width 3.9 mm

plastic shrink small outline package; 14 leads;

body width 5.3 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

Version

SOT27-1

SOT108-1

SOT337-1

SOT402-1

Type number

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