Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC68692
DESCRIPTION
The Philips Semiconductors SCC68692 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is compatible with
SCN68681. It is a single-chip CMOS-LSI communications device
that provides two full-duplex asynchronous receiver/transmitter
channels in a single package. It is compatible with other S68000
family devices and can also interface easily with other
microprocessors. The DUART can be used in a polled or interrupt
driven systems.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruple buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the receiver buffer is full.
Also provided on the SCC68692 are a multipurpose 6-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
•
Parity, framing, and overrun error detection
•
False start bit detection
•
Line break detection and generation
•
Programmable channel mode
–
Normal (full-duplex)
–
Automatic echo
–
Local loopback
–
Remote loopback
–
Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
•
Multi-function 6-bit input port
–
Can serve as clock or control inputs
–
Change of state detection on four inputs
–
Inputs have typically >100 kΩ pull-up resistors
•
Multi-function 8-bit output port
–
Individual bit set/reset capability
•
Versatile interrupt system
–
Outputs can be programmed to be status/interrupt signals
–
Single interrupt output with eight maskable interrupting
conditions
–
Interrupt vector output on interrupt acknowledge
–
Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
FEATURES
•
S68000 bus compatible
•
Dual full-duplex asynchronous receiver/transmitters
•
Quadruple buffered receiver data register
•
Programmable data format:
–
5 to 8 data bits plus parity
–
Odd, even, no parity or force parity
–
1, 1.5 or 2 stop bits programmable in 1/16-bit increments
•
16-bit programmable Counter/Timer
•
Programmable baud rate for each receiver and transmitter
selectable from:
–
22 fixed rates: 50 to 115.2 k baud
–
Non-standard rates to 115.2 kb
–
Non-standard user-defined rate derived from programmable
counter/timer
–
External 1X or 16X clock
•
Maximum data transfer rates: 1X – 1 MB/sec, 16X – 125 kB/sec
•
Automatic wake-up mode for multidrop applications
•
Start-end break interrupt/status
•
Detects break which originates in the middle of a character
•
On-chip crystal oscillator
•
Power down mode
•
Receiver timeout mode
•
Commercial and Industrial temperature range versions
•
TTL compatible
•
Single +5 V power supply
ORDERING INFORMATION
COMMERCIAL
DESCRIPTION
40-Pin (600 mils wide) Plastic Dual In-Line Package (DIP)
44-Pin Plastic Leaded Chip Carrier (PLCC)
V
CC
= +5 V
±
10 %,
T
amb
= 0 to +70
°C
SCC68692C1N40
SCC68692C1A44
INDUSTRIAL
V
CC
= +5 V
±
10 %,
T
amb
= –40 to +85
°C
SCC68692E1N40
SCC68692E1A44
DWG #
SOT129-1
SOT187-2
2004 Mar 03
2
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC68692
PIN DESCRIPTION
SYMBOL
D0–D7
CSN
PIN NO.
TYPE
25,16,24,17
I/O
23,18,22,19
35
I
NAME AND FUNCTION
Data Bus:
Bidirectional 3-State data bus used to transfer commands, data and status between the DUART
and the CPU. D0 is the least significant bit.
Chip Enable:
Active-LOW input signal. When LOW, data transfers between the CPU and the DUART are
enabled on D0–D7 as controlled by the R/WN and A1–A4 inputs. When CEN is HIGH, the DUART places
the D0–D7 lines in the 3-State condition.
Read/Write:
A HIGH input indicates a read cycle and a LOW input indicates a write cycle, when a cycle is
initiated by assertion of the CSN input.
Address Inputs:
Select the DUART internal registers and ports for read/write operations.
Reset:
A LOW level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex
0F, puts OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channels A and B in the inactive
state, with the TxDA and TxDB outputs in the mark (HIGH) state. Resets Test Mode, sets MR pointer to MR1.
Data Transfer Acknowledge:
3-State active-LOW output asserted in write, read, or interrupt cycles to
indicate proper transfer of data between the CPU and the DUART.
Interrupt Request:
Active-LOW, open-drain output which signals the CPU that one or more of the eight
maskable interrupting conditions are true.
Interrupt Acknowledge:
Active-LOW input indicating an interrupt acknowledge cycle. In response, the
DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
Crystal 1:
Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.
Crystal 2:
Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected
although it is permissible to ground it.
Channel A Receiver Serial Data Input:
The least significant bit is received first. “Mark” is HIGH, “space” is LOW.
Channel B Receive Serial Data Input:
The least significant bit is received first. “Mark” is HIGH, “space” is LOW.
Channel A Transmitter Serial Data Output:
The least significant bit is transmitted first. This output is held
in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback mode.
“Mark” is HIGH, “space” is LOW.
Channel B Transmitter Serial Data Output:
The least significant bit is transmitted first. This output is held
in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode.
‘Mark’ is HIGH, ‘space’ is LOW.
Output 0:
General purpose output or Channel A request to send (RTSAN, active-LOW). Can be
deactivated automatically on receive or transmit.
Output 1:
General purpose output or Channel B request to send (RTSBN, active-LOW). Can be
deactivated automatically on receive or transmit.
Output 2:
General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver
1X clock output.
Output 3:
General purpose output or open-drain, active-LOW counter/timer output or Channel B transmitter
1X clock output, or Channel B receiver 1X clock output.
Output 4:
General purpose output or Channel A open-drain, active-LOW, RxRDYAN/FFULLAN output.
Output 5:
General purpose output or Channel B open-drain, active-LOW, RxRDYBN/FFULLBN output.
Output 6:
General purpose output or Channel A open-drain, active-LOW, TxRDYAN output.
Output 7:
General purpose output or Channel B open-drain, active-LOW, TxRDYBN output.
Input 0:
General purpose input or Channel A clear to send active-LOW input (CTSAN). Pin has an internal
V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 1:
General purpose input or Channel B clear to send active-LOW input (CTSBN). Pin has an internal
V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 2:
General purpose input or Channel B receiver external clock input (RxCB), or counter/timer external
clock input. When external clock is used by the receiver, the received data is sampled on the rising edge of
the clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 3:
General purpose input or Channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 4:
General purpose input or Channel A receiver external clock input (RxCA). When the external clock
is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal
V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 5:
General purpose input or Channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Power Supply:
+5 V supply input.
Ground
R/WN
A1–A4
RESETN
8
1,2,5,6
34
I
I
I
DTACKN
INTRN
IACKN
X1/CLK
X2
RxDA
RxDB
TxDA
9
21
37
32
33
31
10
30
O
O
I
I
I
I
I
O
TxDB
11
O
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
IP0
IP1
IP2
29
12
28
13
27
14
26
15
7
4
36
O
O
O
O
O
O
O
O
I
I
I
IP3
2
I
IP4
39
I
IP5
38
I
V
CC
GND
40
20
I
I
2004 Mar 03
5
FPGA/CPLD
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