531SC729M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531SC729M000DGR

531SC729M000DGR: DescriptionLVDS Output Clock Oscillator, 729MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531SC729M000DGR Overview

LVDS Output Clock Oscillator, 729MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531SC729M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	729 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Small hydropower station control and protection circuit

High stability DC power supply circuit diagram

Voice controlled doorbell switch circuit

Programmable time delay circuit circuit diagram

0~20V adjustable regulated power supply composed of μA723

845E computer motherboard circuit diagram_35

Sugar gliders Part ⑩ Sugar glider health monitoring system based on RSL10 - host computer design: Preface The goals of this project are introduced in the project introduction post, the second and third of which are : 2. Sports and health data analysis: Since Xiao Mi is active at night, when we are...; justd0 onsemi and Avnet IoT Innovation Design Competition

About 2407A program burning (please advise again): Please give me some advice, I can't burn the program now.Error: Read status value 0x0001 from symbol PRG_statusFlash algorithm failed during clear operationThis is the error message.MEMORY{PAGE 0:VECS...; sure549 Microcontroller MCU

[Repost] Please don’t be an impetuous embedded system engineer: Copying a post from the Internet: 1. Don't say "Give me a code!" as the first sentence after seeing someone's reply. You should think about why. When you figure it out yourself and refer to other peop...; gjidfo Embedded System

Microinstruction loop problem: There are loop instructions in the tec-2 machine, such as shl DR, but they can only shift one bit at a time. If you want to shift n bits, you need n instructions. I want to design a microprogram based...; lnb19850110 Embedded System

Overcoming the Difficulties of C Language Written and Computer Tests V0.3: Overcoming the Difficulties of C Language Written and Computer Tests V0.3...; 905377346 stm32/stm8

Can someone help me figure out whether this active filter is a voltage-controlled power supply type or a multiple feedback type?: Can someone help me check if this active filter is a voltage-controlled power supply type or a multiple feedback type? Also, if I want to change it to a low-pass filter with a cutoff frequency of 1kHz...; 南木木 Analog electronics

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components