ICS726
12
TO
36 MH
Z
SOT-23 VCXO
Description
Used in conjunction with an external pullable quartz
crystal, this monolithic integrated circuit replaces more
costly hybrid (canned) VCXO devices. The ICS726 is
designed primarily for data and clock recovery
applications such as ADSL modems, set-top box
receivers, and telecom systems.
The frequency of the on-chip VCXO is adjusted by an
external control voltage to the VIN pin. Since VIN is a
high impedance input, it can be driven directly from an
PWM RC integrator circuit. Frequency output increases
with VIN voltage input. The usable range of VIN is 0 to
3.3 V.
Features
•
Uses an inexpensive 12 to 36 MHz external crystal
•
Output frequency range of 12 to 36 MHz
•
On-chip VCXO with guaranteed pull range of ±115
ppm minimum
•
VCXO tuning voltage 0 to 3.3 V
•
Packaged in 6-pin TSOT-23-6
•
Available in Pb (lead) free package
Block Diagram
VDD
VIN
X1
12-36MHz
Pullable
Crystal
X2
Voltage
Controlled
Crystal
Oscillator
12-36MHz
GND
MDS 726 F
I n t e gra te d C i r c u i t S y s t e m s
●
1
525 Race Stre et, San Jo se, CA 9 5126
●
Revision 112905
te l (40 8) 2 97-12 01
●
w w w. i c st . c o m
ICS726
12
TO
36 MH
Z
SOT-23 VCXO
External Component Selection
The ICS726 requires a minimum number of external
components for proper operation.
Required Crystal Parameters:
Nominal Frequency
as required MHz
Initial Accuracy at 25
°
C
-20 min/+20 max ppm
Temperature Stability
-30 min/+30 max ppm
Aging, 1st year
-5 min/+5 max ppm
Aging, 10 years
-20 min/+20 max ppm
Operating Temp. Range, °C
0 min/+25 typ/+70 max
or
Operating Temp. Range, °C -40 min/+25 typ/+85 max
Load Capacitance
10 pf
Shunt Capacitance, C0
7 pF Max
C0/C1 Ratio
270 Max
Equivalent Series Resistance
35
Ω
Max
The third overtone mode of the crystal and all spurs
must be >100 ppm distant from the 3x fundamental
resonance measured with a physical load of 10 pF.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS726. There should be no vias between
the crystal pins and the X1 and X2 device pins. There
should be no signal traces underneath or close to the
crystal. See application note MAN05.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD (pin 4) and GND (pin 2), as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output (CLK,
pin 3) and the load is over 1 inch, series termination
should be used. To series terminate a 50Ω trace (a
commonly used trace impedance) place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Quartz Crystal
The ICS726 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The ICS726 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the ICS726 is designed to have zero frequency
error when the total of on-chip + stray capacitance is 14
pF.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. The need for these capacitors
is determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
The procedure for determining the value of these
capacitors can be found in application note MAN05.
MDS 726 F
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 112905
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS726
12
TO
36 MH
Z
SOT-23 VCXO
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS726. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70°C
-65 to +150°C
260°C
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Reference crystal parameters
Min.
0
+3.15
Typ.
Max.
+70
+3.45
Units
°C
V
Refer to page 3
MDS 726 F
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 112905
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS726
12
TO
36 MH
Z
SOT-23 VCXO
DC Electrical Characteristics
VDD=3.3 V ±5%
, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Short Circuit Current
VIN, VCXO Control Voltage
Symbol
VDD
V
OH
V
OL
V
OH
IDD
I
OS
V
IA
Conditions
I
OH
= -12 mA
I
OL
= 12 mA
I
OH
= -4 mA
Output = 12 MHz,
no load
Min.
3.15
2.4
Typ.
Max.
3.45
0.4
Units
V
V
V
V
VDD-0.4
5
±50
0
3.3
mA
mA
V
AC Electrical Characteristics
VDD = 3.3 V ±5%,
Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Output Frequency
Crystal Pullability,
Note 2
VCXO Gain
Output Rise Time
Output Fall Time
Output Clock Duty
Cycle
Maximum Output
Jitter, short term
Symbol
F
O
F
P
Conditions
0V< VIN < 3.3 V, Note 1
VIN = VDD/2 ± 1 V, Note 1
Min.
12
±115
Typ.
Max. Units
36
MHz
ppm
140
0.8
0.8
40
50
100
1.5
1.5
60
ppm/V
ns
ns
%
ps
t
OR
t
OF
t
D
t
J
0.8 to 2.0 V, C
L
=15 pF
2.0 to 0.8 V, C
L
=15 pF
Measured at 1.4 V, C
L
=15 pF
C
L
=15 pF
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
MDS 726 F
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 112905
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
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