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5962-9461109HXC

Description
Cache SRAM Module, 512KX32, 20ns, CMOS, CPGA66, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66
Categorystorage    storage   
File Size288KB,40 Pages
ManufacturerWhite Microelectronics
Download Datasheet Parametric View All

5962-9461109HXC Overview

Cache SRAM Module, 512KX32, 20ns, CMOS, CPGA66, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66

5962-9461109HXC Parametric

Parameter NameAttribute value
MakerWhite Microelectronics
package instructionHEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66
Reach Compliance Codeunknown
Maximum access time20 ns
Other featuresALSO CONFIGURABLE AS 2M X 8
Spare memory width16
JESD-30 codeS-CPGA-P66
JESD-609 codee4
memory density16777216 bit
Memory IC TypeCACHE SRAM MODULE
memory width32
Number of functions1
Number of terminals66
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize512KX32
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height6.223 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Base Number Matches1
REVISIONS
LTR
F
DESCRIPTION
Figure 1; changed case outline M to be available in either a single or
dual cavity package. Added vendor CAGE code 0EU86 for device
types 05 through 10. -sld
Added device types 11 through 16.
Add note to paragraph 1.2.2 and table I, conditions. Add thermal
resistance, junction-to-case (θ
JC
) for all case outlines. Add case
outline 9.
Table I, I
CC
change maximum limits and I
SB
change maximum limits.
Figure 1, case outline M, correct diagram adding "c" dimension, lead
thickness and change dimension A2 maximum from 0.020" to 0.025".
Figure 1, case outline 9, minimum dimension for D2/E2, change
0.990 inches to 0.980 inches and 25.15 mm to 24.89 mm.
Table I; Operating supply current (I
CC
) changed the maximum limit for
device types 9 and 15 at f = 50 MHz from 700 mA to 725 mA and for
device types 10 and 16 at f = 58.8 MHz from 700 mA to 750 mA. -sld
Added device types 17 through 20. -sld
Added case outline A. -sld
Added case outline B. Added note to paragraph 1.2.4. -sld
Table I; Changed the I
OL
from 8 mA to 6 mA for device types 07-10
and 13 -20 for the V
OL
test. Editorial changes throughout. -sld
DATE (YR-MO-DA)
99-04-22
APPROVED
K. A. Cottongim
G
H
99-08-18
00-04-06
Raymond Monnin
Raymond Monnin
J
00-06-19
Raymond Monnin
K
L
01-5-16
01-12-21
Raymond Monnin
Raymond Monnin
M
N
P
R
02-11-18
03-02-24
03-12-19
04-05-03
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
R
15
R
16
R
17
R
18
REV
SHEET
PREPARED BY
Gary Zahn
CHECKED BY
Michael C. Jones
R
19
R
20
R
21
R
1
R
22
R
2
R
23
R
3
R
24
R
4
R
25
R
5
R
26
R
6
R
27
R
7
R
28
R
8
R
29
R
9
R
30
R
10
R
31
R
11
R
12
R
13
R
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, HYBRID, MEMORY,
DIGITAL, 512K x 32-BIT, STATIC RANDOM
ACCESS MEMORY, CMOS
SIZE
A
SHEET
CAGE CODE
DRAWING APPROVAL DATE
95-11-13
REVISION LEVEL
R
67268
1 OF
31
5962-94611
5962-E251-04
DSCC FORM 2233
APR 97
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