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IDT72225LB15TFGI8

Description
FIFO, 1KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64
Categorystorage    storage   
File Size324KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

IDT72225LB15TFGI8 Overview

FIFO, 1KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64

IDT72225LB15TFGI8 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionLFQFP,
Contacts64
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time10 ns
period time15 ns
JESD-30 codeS-PQFP-G64
JESD-609 codee3
length10 mm
memory density18432 bit
memory width18
Humidity sensitivity level3
Number of functions1
Number of terminals64
word count1024 words
character code1000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1KX18
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width10 mm
Base Number Matches1
CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
IDT72205LB, IDT72215LB,
IDT72225LB, IDT72235LB,
IDT72245LB
FEATURES:
256 x 18-bit organization array (IDT72205LB)
512 x 18-bit organization array (IDT72215LB)
1,024 x 18-bit organization array (IDT72225LB)
2,048 x 18-bit organization array (IDT72235LB)
4,096 x 18-bit organization array (IDT72245LB)
10 ns read/write cycle time
Empy and Full flags signal FIFO status
Easy expandable in depth and width
Asynchronous or coincident read and write clocks
Programmable Almost-Empty and Almost-Full flags with
default settings
Half-Full flag capability
Dual-Port zero fall-through time architecture
Output enable puts output data bus in high-impedence state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
and plastic leaded chip carrier (PLCC)
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
DESCRIPTION:
write controls. These FIFOs are applicable for a wide variety of data buffering
needs, such as optical disk controllers, Local Area Networks (LANs), and
interprocessor communication.
These FIFOs have 18-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is read
into the synchronous FIFO on every clock when
WEN
is asserted. The output
port is controlled by another clock pin (RCLK) and another enable pin (REN).
The read clock can be tied to the write clock for single clock operation or the
two clocks can run asynchronous of one another for dual-clock operation. An
Output Enable pin (OE) is provided on the read port for three-state control of
the output.
The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF),
and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The
offset loading of the programmable flags is controlled by a simple state machine,
and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available
when the FIFO is used in a single device configuration.
These devices are depth expandable using a Daisy-Chain technique. The
XI
and
XO
pins are used to expand the FIFOs. In depth expansion configu-
ration, First Load (FL) is grounded on the first device and set to HIGH for all
other devices in the Daisy Chain.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated
using high-speed submicron CMOS technology.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high
speed, low-power First-In, First-Out (FIFO) memories with clocked read and
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0-D17
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
FLAG
LOGIC
/(
READ POINTER
READ CONTROL
LOGIC
)
(
)/
EXPANSION LOGIC
OUTPUT REGISTER
RESET LOGIC
Q0-Q17
RCLK
2766 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
MARCH 2013
DSC-2766/3
©2013
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
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