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74LVT574, 74LVTH574 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
January 2008
74LVT574, 74LVTH574
Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Features
■
Input and output interface capability to systems at
■
General Description
The LVT574 and LVTH574 are high-speed, low-power
octal D-type flip-flop featuring separate D-type inputs for
each flip-flop and 3-STATE outputs for bus-oriented
applications. A buffered Clock (CP) and Output Enable
(OE) are common to all flip-flops.
The LVTH574 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal flip-flops are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT574 and
LVTH574 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
■
■
■
■
■
■
5V V
CC
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH574),
also available without bushold feature (74LVT574)
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink –32mA/+64mA
Functionally compatible with the 74 series 574
Latch-up performance exceeds 500mA
ESD performance:
– Human-body model
>
2000V
– Machine model
>
200V
– Charged-device model
>
1000V
Ordering Information
Order Number
74LVT574WM
74LVT574SJ
74LVT574MSA
74LVT574MTC
74LVTH574WM
74LVTH574SJ
74LVTH574MSA
74LVTH574MTC
Package
Number
M20B
M20D
MSA20
MTC20
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation
74LVT574, 74LVTH574 Rev. 1.6.0
www.fairchildsemi.com
74LVT574, 74LVTH574 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
D
0
–D
7
CP
OE
O
0
–O
7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
Functional Description
The LVT574 and LVTH574 consist of eight edge-
triggered flip-flops with individual D-type inputs and
3-STATE true outputs. The buffered clock and buffered
Output Enable are common to all flip-flops. The eight
flip-flops will store the state of their individual D-type
inputs that meet the setup and hold time requirements
on the LOW-to-HIGH Clock (CP) transition. With the Out-
put Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When the OE is HIGH, the
outputs go to the high impedance state. Operation of the
OE input does not affect the state of the flip-flops.
Truth Table
Inputs
D
n
H
L
X
X
L
X
Outputs
OE
L
L
L
H
CP
O
n
H
L
O
o
Z
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
O
o
=
Previous O
o
before HIGH to LOW of CP
©1999 Fairchild Semiconductor Corporation
74LVT574, 74LVTH574 Rev. 1.6.0
www.fairchildsemi.com
2
74LVT574, 74LVTH574 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1999 Fairchild Semiconductor Corporation
74LVT574, 74LVTH574 Rev. 1.6.0
www.fairchildsemi.com
3
74LVT574, 74LVTH574 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
Supply Voltage
DC Input Voltage
DC Output Voltage
Output in 3-STATE
Parameter
Rating
–0.5V to +4.6V
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to +7.0V
–50mA
–50mA
64mA
128mA
±64mA
±128mA
–65°C to +150°C
Output in HIGH or LOW State
(1)
I
IK
I
OK
I
O
DC Input Diode Current, V
I
<
GND
DC Output Diode Current, V
O
<
GND
DC Output Current, V
O
>
V
CC
Output at HIGH State
Output at LOW State
I
CC
I
GND
T
STG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Note:
1. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
I
OH
I
OL
T
A
∆
t /
∆
V
Supply Voltage
Input Voltage
Parameter
Min
2.7
0
Max
3.6
5.5
–32
64
Units
V
V
mA
mA
°C
ns/V
HIGH-Level Output Current
LOW-Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
–40
0
85
10
©1999 Fairchild Semiconductor Corporation
74LVT574, 74LVTH574 Rev. 1.6.0
www.fairchildsemi.com
4
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