HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
Features
PRELIMINARY
IDT70V07S/L
x
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
Commercial: 25/35/55ns (max.)
Low-power operation
IDT70V07S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
IDT70V07L
Active: 300mW (typ.)
Standby: 660
µ
W (typ.)
IDT70V07 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
x
x
x
x
x
x
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 80-pin TQFP
Description
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static RAM. The
IDT70V07 is designed to be used as a stand-alone 256K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-
or-more word systems. Using the IDT MASTER/SLAVE Dual-Port
RAM approach in 16-bit or wider memory system applications results
in full-speed, error-free operation without the need for additional
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
14L
A
0L
(1,2)
I/O
Control
I/O
0R
-I/O
7R
,
BUSY
R
Address
Decoder
15
(1,2)
MEMORY
ARRAY
15
Address
Decoder
A
14R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R(2)
2943 drw 01
JUNE 1999
1
DSC 2943/5
©1998 Integrated Device Technology, Inc.
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature controlled by
CE
permits the on-chip circuitry of each port
to enter a very low standby power mode.
Fabricated using IDTs CMOS high-performance technology, these
devices typically operate on only 300mW of power.
The IDT70V07 is packaged in a ceramic 68-pin PGA and PLCC and
a 80-pin thin quad flatpack (TQFP).
Pin Configurations
(1,2,3)
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
1L
I/O
0L
N/C
OE
L
R/W
L
SEM
L
CE
L
A
14L
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
IDT70V07J
J68-1
(4)
68-Pin PLCC
Top View
(5)
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
2943 drw 02
I/O
7R
N/C
OE
R
R/W
R
SEM
R
CE
R
A
14R
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
INDEX
N/C
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
N/C
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
2
I/O
7R
N/C
OE
R
R/W
R
SEM
R
CE
R
N/C
A
14R
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
N/C
N/C
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
57
4
56
5
55
6
54
7
70V07PF
53
8
PN80-1
(4)
9
52
10
51
80-Pin TQFP
50
11
Top View
(5)
49
12
48
13
14
47
15
46
16
45
44
17
43
18
19
42
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
I/O
1L
I/O
0L
N/C
OE
L
R/W
L
SEM
L
CE
L
N/C
A
14L
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
,
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
2943 drw 03
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
51
11
53
A
7L
55
A
9L
A
5L
52
A
6L
54
A
8L
50
A
4L
49
A
3L
48
A
2L
47
A
1L
46
44
42
A
0L
BUSY
L
M/S
40
38
INT
R
A
1R
36
A
3R
35
A
4R
32
A
7R
30
A
9R
28
A
11R
26
GND
34
A
5R
33
A
6R
31
A
8R
29
A
10R
27
A
12R
10
45
43
41
39
37
INT
L
GND
BUSY
R
A
0R
A
2R
09
08
57
56
A
11L
A
10L
59
58
V
CC
A
12L
61
60
A
13L
07
IDT70V07G
G68-1
(4)
68-Pin PGA
Top View
(5)
06
A
14L
05
63
62
SEM
L
CE
L
65
64
OE
L
R/W
L
67
66
I/O
0L
N/C
1
3
68
I/O
1L
I/O
2L
I/O
4L
2
4
I/O
3L
I/O
5L
B
C
24
25
A
14R
A
13R
22
23
SEM
R
CE
R
20
OE
R
21
R/W
R
04
03
02
5
7
9
11
13
15
GND I/O
7L
GND I/O
1R
V
CC
I/O
4R
6
I/O
6L
D
8
10
12
14
16
V
CC
I/O
0R
I/O
2R
I/O
3R
I/O
5R
E
F
G
H
J
18
19
I/O
7R
N/C
17
I/O
6R
K
01
A
INDEX
L
2943 drw 04
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
(1,2)
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
14L
I/O
0L
- I/O
7L
SEM
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
14R
I/O
0R
- I/O
7R
SEM
R
INT
R
BUSY
R
M/S
V
CC
GND
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2943 tbl 01
Names
3
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
2943 tbl 02
Mode
NOTE:
1. A
0L
A
14L
≠
A
0R
A
14R
Truth Table II: Semaphore Read/Write Control
Inputs
(1)
CE
H
H
L
R/W
H
↑
X
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-7
DATA
OUT
DATA
IN
____
Mode
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
2943 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O's (I/O
0
-I/O
7
). These eight semaphores are addressed by A
0
-A
2
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +4.6
Unit
V
Maximum Operating Temperature
and Supply Voltage
(1,2)
Grade
Commercial
Ambient Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
3.3V
+
0.3
3.3V
+
0.3
2943 tbl 05
T
BIAS
T
STG
I
OUT
-55 to +125
-55 to +125
50
o
C
C
Industrial
o
mA
2943 tbl 04
NOTES:
1. This is the parameter T
A
.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 0.3V.
Recommended DC Operating
Conditions
(2)
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
CC
+0.3
(2)
0.8
Unit
V
V
V
V
2943 tbl 06
Capacitance
(1)
Symbol
C
IN
C
OUT
Input Capacitance
(T
A
= +25°C, f = 1.0MHz) TQFP Only
Parameter
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2943 tbl 07
Output Capacitance
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.3V.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
4
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V ± 0.3V)
70V07S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.6V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
70V07L
Min.
___
___
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2943 tbl 08
2.4
2.4
NOTE:
1. At V
CC
< 2.0V, input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,6)
(V
CC
= 3.3V ± 0.3V)
70V07X25
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Test Condition
CE
= V
IL
, Outputs Open
SEM
= V
IL
f = f
MAX
(3)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
(2)
100
100
____
____
70V07X35
Com'l Only
Typ.
(2)
90
90
____
____
70V07X55
Com'l Only
Typ.
(2)
90
90
____
____
Max.
170
140
____
____
Max.
140
120
____
____
Max.
140
120
____
____
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
R
=
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(3)
14
12
____
____
30
24
____
____
12
10
____
____
30
24
____
____
12
10
____
____
30
24
____
____
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Open,
f=f
MAX
(3)
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
- 0.2V
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Open,
f = f
MAX
(3)
50
50
____
____
95
85
____
____
45
45
____
____
87
75
____
____
45
45
____
____
87
75
____
____
mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
1.0
0.2
____
____
6
3
____
____
1.0
0.2
____
____
6
3
____
____
1.0
0.2
____
____
6
3
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
60
60
____
____
90
80
____
____
55
55
____
____
85
74
____
____
55
55
____
____
85
74
____
____
mA
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. V
CC
= 3.3V, T
A
= +25°C, and are not production tested. I
CCDC
= 80mA (Typ.)
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ t
RC,
and using AC Test Conditions" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
2943 tbl 09
5
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