40-Channel, 14-Bit, Parallel and
Serial Input, Bipolar Voltage-Output DAC
AD5379
FEATURES
40-channel DAC in 13 mm × 13 mm 108-lead CSPBGA
Guaranteed monotonic to 14 bits
Buffered voltage outputs
Output voltage span of 3.5 V × V
REF
(+)
Maximum output voltage span of 17.5 V
System calibration function allowing user-programmable
offset and gain
Pseudo differential outputs relative to REFGND
Clear function to user-defined REFGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
DAC increment/decrement mode
Channel grouping and addressing features
Interface options:
Parallel interface
DSP/microcontroller-compatible, 3-wire serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
SDO daisy-chaining option
Power-on reset
Digital reset (RESET pin and soft reset function)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
FUNCTIONAL BLOCK DIAGRAM
V
CC
POWER-ON
RESET
RESET
FIFOEN
DCEN/WR
SYNC/CS
14
V
DD
V
SS
AGND
DGND
LDAC
V
BIAS
V
REF
1(+) V
REF
1(–) REFGND A1
VBIAS
CLR
AD5379
/
FIFO
REG0
REG1
DB13
SCLK/DB12
DIN/DB11
INPUT
14
REG
0–1
14
/
m REG0–1
c REG0–1
14
/
DAC
14
REG
0–1
VOUT0
/
DAC 0–1
VOUT1
/
14
INTERFACE
DB0
A7
/
INPUT 14
REG
2
14
/
m REG2
c REG2
14
/
DAC 14
REG
2
/
DAC 2
VOUT2
VOUT3
VOUT4
VOUT5
A0
SER/PAR
DIN
SCLK
SDO
STATE MACHINE
14
/
14
/
/
INPUT
14
REG
7
14
/
m REG7
c REG7
14
/
DAC
14
REG
7
VOUT6
/
DAC 7
VOUT7
/
/
REFGND B1
REFGND B2
REFGND C1
REFGND C2
REFGND D1
REFGND D2
BUSY
14
14
/
INPUT
14
REG
8–9
14
/
DAC
14
REG
8–9
VOUT8
/
DAC 8–9
VOUT9
VOUT10
/
m REG8–9
c REG8–9
VOUT39
V
REF
2(+) V
REF
2(–) REFGND A2
Figure 1.
AD5379—Protected by U.S. Patent No. 5,969,657.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2009 Analog Devices, Inc. All rights reserved.
03165-001
×4
AD5379
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 3
Specifications..................................................................................... 4
AC Characteristics........................................................................ 5
Timing Characteristics..................................................................... 6
Serial Interface .............................................................................. 6
Parallel Interface ........................................................................... 9
Absolute Maximum Ratings.......................................................... 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Terminology .................................................................................... 15
Typical Performance Characteristics ........................................... 16
Functional Description .................................................................. 18
DAC Architecture—General ..................................................... 18
Channel Groups .......................................................................... 18
Transfer Function ....................................................................... 18
V
BIAS
Function ............................................................................. 19
Reference Selection .................................................................... 19
Calibration................................................................................... 20
Clear Function ............................................................................ 20
BUSY and LDAC Functions...................................................... 20
FIFO vs. Non-FIFO Operation................................................. 21
BUSY Input Function ................................................................ 21
Power-On Reset Function ......................................................... 21
RESET Input Function .............................................................. 21
Increment/Decrement Function .............................................. 21
Interfaces.......................................................................................... 22
Parallel Interface ......................................................................... 22
Serial Interface ............................................................................ 22
Data Decoding ................................................................................ 24
Address Decoding .......................................................................... 25
Power Supply Decoupling ............................................................. 26
Power-On .................................................................................... 26
Typical Application Circuit ........................................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/09—Rev. A t o Rev. B
Changes to Table 14 ........................................................................ 24
1/05—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Change to Transfer Function Equation ....................................... 18
4/04—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD5379
GENERAL DESCRIPTION
The AD5379 contains 40 14-bit DACs in one CSPBGA package.
The AD5379 provides a bipolar output range determined by the
voltages applied to the V
REF
(+) and V
REF
(−) inputs. The maxi-
mum output voltage span is 17.5 V, corresponding to a bipolar
output range of −8.75 V to +8.75 V, and is achieved with reference
voltages of V
REF
(−) = −3.5 V and V
REF
(+) = +5 V.
The AD5379 offers guaranteed operation over a wide V
SS
/V
DD
supply range from ±11.4 V to ±16.5 V. The output amplifier
headroom requirement is 2.5 V operating with a load current of
1.5 mA, and 2 V operating with a load current of 0.5 mA.
The AD5379 contains a double-buffered parallel interface in
which 14 data bits are loaded into one of the input registers
under the control of the WR, CS, and DAC Channel Address
Pins A0 to A7. It also has a 3-wire serial interface that is com-
patible with SPI®, QSPI™, MICROWIRE™, and DSP® interface
standards and can handle clock speeds of up to 50 MHz.
The DAC outputs are updated upon reception of new data into
the DAC registers. All the outputs can be simultaneously updated
by taking the LDAC input low. Each channel has a programmable
gain and an offset adjust register.
Each DAC output is gained and buffered on-chip with respect
to an external REFGND input. The DAC outputs can also be
switched to REFGND via the CLR pin.
Table 1. High Channel Count, Low Voltage, Single-Supply DACs
Model
AD5380BST-5
AD5380BST-3
AD5381BST-5
AD5381BST-3
AD5384BBC-5
AD5384BBC-3
AD5382BST-5
AD5382BST-3
AD5383BST-5
AD5383BST-3
AD5390BST-5
AD5390BCP-5
AD5390BST-3
AD5390BCP-3
AD5391BST-5
AD5391BCP-5
AD5391BST-3
AD5391BCP-3
AD5392BST-5
AD5392BCP-5
AD5392BST-3
AD5392BCP-3
Resolution
14 bits
14 bits
12 bits
12 bits
14 bits
14 bits
14 bits
14 bits
12 bits
12 bits
14 bits
14 bits
14 bits
14 bits
12 bits
12 bits
12 bits
12 bits
14 bits
14 bits
14 bits
14 bits
AV
DD
Range
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
Output Channels
40
40
40
40
40
40
32
32
32
32
16
16
16
16
16
16
16
16
8
8
8
8
Linearity Error (LSB)
±4
±4
±1
±1
±4
±4
±4
±4
±1
±1
±3
±3
±4
±4
±1
±1
±1
±1
±3
±3
±4
±4
Package Description
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead CSPBGA
100-Lead CSPBGA
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
Package Option
ST-100
ST-100
ST-100
ST-100
BC-100
BC-100
ST-100
ST-100
ST-100
ST-100
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
Rev. B | Page 3 of 28
AD5379
SPECIFICATIONS
V
CC
= 2.7 V to 5.5 V; V
DD
= 11.4 V to 16.5 V; V
SS
= −11.4 V to −16.5 V; V
REF
(+) = 5 V; V
REF
(−) = −3.5 V; AGND = DGND = REFGND = 0 V;
V
BIAS
= 5 V; C
L
= 200 pF to GND; R
L
= 11 kΩ to 3 V; gain = 1; offset = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
VOUT Temperature Coefficient
DC Crosstalk
2
REFERENCE INPUTS
2
V
REF
(+) DC Input Impedance
V
REF
(−) DC Input Impedance
V
REF
(+) Input Current
V
REF
(+) Range
V
REF
(−) Range
REFGND INPUTS
2
DC Input Impedance
Input Range
OUTPUT CHARACTERISTICS
2
Output Voltage Range
Short-Circuit Current
Load Current
Capacitive Load
DC Output Impedance
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current (with pull-up/pull-down)
Input Current (no pull-up/pull-down)
Input Capacitance
2
DIGITAL OUTPUTS (BUSY, SDO)
Output Low Voltage
Output High Voltage (SDO)
High Impedance Leakage Current
High Impedance Output Capacitance
2
POWER REQUIREMENTS
V
CC
V
DD
V
SS
A Version
1
14
±3
±2.5
−1/+1.5
±12
±5
±12
±8
±8
±1/±5
5
0.5
1
8
±10
1.5/5
−3.5/0
80
±0.5
V
SS
+ 2/V
SS
+ 2.5
V
DD
− 2/V
DD
− 2.5
15
±1.5
2200
1
1.7
2.0
0.8
±8
±1
10
0.5
V
CC
− 0.5
−70
10
2.7/5.5
8.5/16.5
−3/−16.5
Unit
Bits
LSB max
LSB max
LSB max
mV max
mV max
mV max
mV max
mV max
mV typ/max
ppm FSR/°C typ
mV max
MΩ min
kΩ min
μA max
V min/max
V min/max
kΩ min
V min/max
V min
V max
mA max
mA max
pF max
Ω max
V min
V min
V max
μA max
μA max
pF max
V max
V min
μA max
pF typ
V min/max
V min/max
V min/max
Test Conditions/Comments
2
−40°C to +85°C
0°C to 70°C
Guaranteed monotonic by design over temperature
−40°C to +85°C
0°C to 70°C
−40°C to +85°C
0°C to 70°C
−40°C to +85°C
0°C to 70°C
Includes linearity, offset, and gain drift (see Figure 11)
Typically 100 μV
Typically 100 MΩ
Typically 12 kΩ
Per input (typically ±30 nA)
±2% for specified operation
±2% for specified operation
Typically 120 kΩ
I
LOAD
= ±0.5 mA/±1.5 mA
I
LOAD
= ±0.5 mA/±1.5 mA
JEDEC compliant
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
V
CC
= 2.7 V to 5.5 V
SER/PAR, FIFOEN, and RESET pins only
All other digital input pins
Sinking 200 μA
Sourcing 200 μA
SDO only
Rev. B | Page 4 of 28
AD5379
Parameter
Power Supply Sensitivity
2
∆ Full Scale/∆ V
DD
∆ Full Scale/∆ V
SS
∆ Full Scale/∆ V
CC
I
CC
I
DD
I
SS
Power Dissipation
Power Dissipation Unloaded (P)
Power Dissipation Loaded (P
TOTAL
)
Junction Temperature
A Version
1
−75
−75
−90
5
28
23
850
2000
130
Unit
dB typ
dB typ
dB typ
mA max
mA max
mA max
mW max
mW max
°C max
Test Conditions/Comments
2
V
CC
= 5.5 V, V
IH
= V
CC
, V
IL
= GND
Outputs unloaded (typically 20 mA)
Outputs unloaded (typically 15 mA)
V
DD
= 16.5 V, V
SS
= −16.5 V
P
TOTAL
= P + Σ(V
DD
− V
O
) × I
SOURCE
+ Σ(V
O
− V
SS
) × I
SINK
T
J
= T
A
+ P
TOTAL
× θ
J 3
1
2
Temperature range for A Version: −40°C to +85°C. Typical specifications are at 25°C.
Guaranteed by design and characterization, not production tested.
3
Where
θ
J
represents the package thermal impedance.
AC CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V; V
DD
= 11.4 V to 16.5 V; V
SS
= −11.4 V to −16.5 V; V
REF
(+) = 5 V; V
REF
(−) = −3.5 V; AGND = DGND = REFGND = 0 V;
V
BIAS
= 5 V; C
L
= 220 pF; R
L
= 11 kΩ to 3 V; gain = 1; offset = 0 V.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
A Version
1
20
30
1
20
15
100
40
10
0.1
1
350
Unit
μs typ
μs max
V/μs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)
1/2
typ
Test Conditions/Comments
Full-scale change to ±1/2 LSB
DAC latch contents alternately loaded with all 0s and all 1s
V
REF
(+) = 2 V p-p, (1 V
BIAS
) 1 kHz, V
REF
(−) = −1 V
Between DACs inside a group (see the Terminology section)
Between DACs from different groups
Effect of input bus activity on DAC output under test
V
REF
(+) = V
REF
(−) = 0 V
1
Guaranteed by design and characterization, not production tested.
Rev. B | Page 5 of 28
京公网安备 11010802033920号
EEWORLD
