XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JUNE 2007
REV. 1.0.2
GENERAL DESCRIPTION
The XRT83L38 is a fully integrated Octal (eight
channel) long-haul and short-haul line interface unit
for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or
120Ω, or J1 110Ω applications.
In long-haul applications the XRT83L38 accepts
signals that have been attenuated from 0 to 36dB at
772kHz in T1 mode (equivalent of 0 to 6000 feet of
cable loss) or 0 to 43dB at 1024kHz in E1 mode.
In T1 applications, the XRT83L38 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements as
well as for Channel Service Units (CSU) Line Build
Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB
as required by FCC rules. It also provides
programmable transmit pulse generators for each
channel that can be used for output pulse shaping
allowing performance improvement over a wide
variety of conditions (The arbitrary pulse generators
are available in both T1 and E1 modes).
The XRT83L38 provides both a parallel
Host
microprocessor interface as well as a
Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. An on-chip
crystal-less jitter attenuator with a 32 or 64 bit FIFO
can be placed either in the receive or the transmit
path with loop bandwidths of less than 3Hz. The
XRT83L38 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75Ω,
100Ω, 110Ω and 120Ω for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.
APPLICATIONS
•
T1 Digital Cross-Connects (DSX-1)
•
ISDN Primary Rate Interface
•
CSU/DSU E1/T1/J1 Interface
•
T1/E1/J1 LAN/WAN Routers
•
Public switching Systems and PBX Interfaces
•
T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT83L38 T1/E1/J1 LIU (H
OST
M
ODE
)
MCLKE1
MCLKT1
MASTER CLOCK SYNTHESIZER
MCLKOUT
One of Eight channels, CHANNEL_n - (n= 0:7)
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TAOS
ENABLE
TX FILTER
& PULSE
SHAPER
DFM
DRIVE
MONITOR
LINE
DRIVER
DMO_n
TTIP_n
TRING_n
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
LBO[3:0]
JA
SELECT
QRSS ENABLE
QRSS
DETECTOR
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
LOCAL
ANALOG
LOOPBACK
TXON_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
NETWORK
LOOP
DETECTOR
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
RX
EQUALIZER
RTIP_n
RRING_n
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
RLOS_n
HW/HOST
WR_R/W
RD_DS
ALE_AS
CS
RDY_DTACK
INT
TEST
MICROPROCESSOR CONTROLLER
ICT
μPTS1
μPTS2
D[7:0]
μPCLK
A[7:0]
RESET
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
F
IGURE
2. B
LOCK
D
IAGRAM OF THE
XRT83L38 T1/E1/J1 LIU (H
ARDWARE
M
ODE
)
MCLKE1
MCLKT1
CLKSEL[2:0]
MASTER CLOCK SYNTHESIZER
MCLKOUT
TAOS_n
One of Eight Channels, CHANNEL_n - (n=0 : 7)
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX FILTER
& PULSE
SHAPER
DFM
DRIVE
MONITOR
DMO_n
TTIP_n
TRING_n
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
LINE
DRIVER
LBO[3:0]
JA
SELECT
QRSS ENABLE
QRSS
DETECTOR
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
LOCAL
ANALOG
LOOPBACK
TXON_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
NETWORK
LOOP
DETECTOR
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
RX
EQUALIZER
RTIP_n
RRING_n
LOOP1_n
LOOP0_n
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
RLOS_n
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
TEST
ICT
RESET
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
HARWARE CONTROL
FEATURES
•
Fully integrated eight channel long-haul or short-haul transceivers for E1,T1 or J1 applications
•
Adaptive Receive Equalizer for up to 36dB cable attenuation
•
Programable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces
•
Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform
generator for transmit output pulse shaping available for both T1 and E1 modes
•
Transmit Line Build-Outs (LBO) for T1 long-haul application from 0dB to -22.5dB in three 7.5dB steps
•
Selectable receiver sensitivity from 0 to 36dB cable loss for T1 @772kHz and 0 to 43dB for E1 @1024kHz
•
Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for
E1 and 0 to 3dB of cable attenuation for T1 modes
•
Supports 75Ω and 120Ω (E1), 100Ω (T1) and 110Ω (J1) applications
•
Internal and/or external impedance matching for 75Ω, 100Ω, 110Ω and 120Ω
•
Tri-State transmit output and receive input capability for redundancy applications
•
Provides High Impedance for Tx and Rx during power off
•
Transmit return loss meets or exceeds ETSI 300-166 standard
•
On-chip digital clock recovery circuit for high input jitter tolerance
•
Crystal-less digital jitter attenuator with 32-bit or 64-bit FIFO selectable either in transmit or receive path
•
On-chip frequency multiplier generates T1 or E1 Master clocks from variety of external clock sources
•
High receiver interference immunity
•
On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO)
•
Receive loss of signal (RLOS) output
2
XRT83L38
REV. 1.0.2
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
•
On-chip HDB3/B8ZS/AMI encoder/decoder functions
•
QRSS pattern generator and detection for testing and monitoring
•
Error and Bipolar Violation Insertion and Detection
•
Receiver Line Attenuation Indication Output in 1dB steps
•
Network Loop-Code Detection for automatic Loop-Back Activation/Deactivation
•
Transmit All Ones (TAOS) and In-Band Network Loop Up and Down code generators
•
Supports Local Analog, Remote, Digital and Dual Loop-Back Modes
•
Meets or exceeds T1 and E1 short-haul and long-haul network access specifications in ITU G.703, G.775,
G.736 and G.823; TR-TSY-000499; ANSI T1.403 and T1.408; ETSI 300-166 and AT&T Pub 62411
•
Supports both
Hardware
and
Host
(parallel Microprocessor) interface for programming
•
Programmable Interrupt
•
Low power dissipation
•
Logic inputs accept either 3.3V or 5V levels
•
Single 3.3V Supply Operation
•
225 ball BGA package
•
-40°C to +85°C Temperature Range
ORDERING INFORMATION
P
ART
N
UMBER
XRT83L38IB
P
ACKAGE
225 Ball BGA
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
3
A
CLKSEL0
DVDD
A[1]
A[3]
A[7]
TXON_0 JASEL0
TCLK_2
RLOS_3
RCLK_3
NC4
TAOS_1
CS
CLKSEL1
DGND
A[2]
A[6]
TX0N_3 JASEL1 TPOS_2 TNEG_3
RNEG_3
RPOS_3
NC12
NC1
RNEG_0
TCLK_1
TPOS_1
TAOS_2 RDY_DTACK ALE_AS
XRT83L38
B
TAOS_3
RD_DS
CLKSEL2 DGND_PDR
A[0]
A[5]
TXON_2 DMO_3 TCLK_3
DMO_2
TTIP_3
TGND_3
RTIP_3
NC5
RPOS_0
RCLK_0
TCLK_0
TNEG_1
C
TAOS_0
WR_R/W DGND_DR
DVDD_DR DVDD_PDR
A[4]
TXON_1 TNEG_2 TPOS_3 RPOS_2 RVDDD_3
RGND_3
RRING_3
RTIP_0
RVDD_0
RLOS_0
TNEG_0
TPOS_0
D
TGND_2
TRING_3
TVDD_3
NC11
RRING_0
RGND_0
TGND_0
DMO_1
DMO_0
F
IGURE
3. P
ACKAGE
P
IN
O
UT
E
TRING_2
TVDD_2
TTIP_2
NC6
TRING_O
TTIP_0
TVDD_0
RVDD_1
F
DGND_DR RVDD_2
RGND_2
RRING_1
TGND_1
TRING_1
TVDD_1
RRING_2
G
RLOS_2
RCLK_2
RTIP_1
RPOS_1
RGND_1
TTIP_1
RTIP_2
H
RLOS_6
MCLKOUT RNEG_1
RCLK_1
RLOS_1
DGND_µP
RNEG_2
J
MCLKE1 VDDPLL_2 VDDPLL_1 DVDD_DR
PTS1
AGND_BIAS
GAUGE
XRT83L38
(Top View)
225 Ball BGA
DVDD_DR
RXON
AVDD_BIAS DVDDD_µP
K
MCLKT1 DGND_DR GNDPLL_1
SR_DR
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
4
TAOS_7
D[0]
DGND_PDR DVDD_DR
RXRES1
TAOS_4
D[7]
RESET
TAOS_5
D[6]
D[2]
D[1]
DVDD_PDR RXTSEL
TEST
TXON_5 TNEG_6
TAOS_6
D[5]
D[4]
D[3]
RXRES0
TXTSEL
ICT
TXON_4 DMO_7
L
RTIP_5
RLOS_5
RCLK_5
GNDPLL_2
PTS2
INT
RPOS_6
RTIP_6
M
RRING_5
RGND_5
RPOS_5
RNEG_5
RCLK_6
RNEG_6
RGND_6
RRING_6
N
NC7
TTIP_5
RVDD_5
TRING_5
TVDD_6
TTIP_6
RVDD_6
Nc10
P
TVDD_5
TRING_4
TGND_5
DMO_5
TVDD_7
TTIP_7
TRING_7
NC9
R
NC8
TTIP_4
TGND_4
TVDD_4
DMO_4
TERSEL0 TXON_6 TXON_7 TNEG_7 TRING_6
TGND_7
RGND_7
RRING_7
T
RRING_4
RGND_4
TCLK_4
RNEG_4
TCLK_5
DGND_DR HW_HOST TERSEL1 RXMUTE µPCLK TPOS_7 RLOS_7
TGND_6
RPOS_7
RTIP_7
U
RTIP_4
RPOS_4
RCLK_4
TNEG_4
TPOS_5
TCLK_7
RCLK_7
DMO_6
RVDD_7
V
6
7
8
NC2
RVDD_4
RLOS_4
TPOS_4
TNEG_5
TPOS_6
TCLK_6
RNEG_7
NC3
REV. 1.0.2
1
2
3
4
5
9
10
11
12
13
14
15
16
17
18
XRT83L38
REV. 1.0.2
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
A
PPLICATIONS
................................................................................................................................ 1
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT83L38 T1/E1/J1 LIU (H
OST
M
ODE
) ............................................................. 1
F
IGURE
2. B
LOCK
D
IAGRAM OF THE
XRT83L38 T1/E1/J1 LIU (H
ARDWARE
M
ODE
) .................................................... 2
F
EATURES
...................................................................................................................................... 2
ORDERING INFORMATION .................................................................................................................... 3
F
IGURE
3. P
ACKAGE
P
IN
O
UT
.................................................................................................................................... 4
TABLE OF CONTENTS ..................................................................................................... I
PIN DESCRIPTION BY FUNCTION................................................................................... 5
R
ECEIVE
S
ECTIONS
........................................................................................................................ 5
T
RANSMITTER
S
ECTIONS
................................................................................................................ 7
M
ICROPROCESSOR
I
NTERFACE
..................................................................................................... 11
JITTER
A
TTENUATOR
..................................................................................................................... 14
C
LOCK
S
YNTHESIZER
................................................................................................................... 14
A
LARM
F
UNCTIONS
/R
EDUNDANCY
S
UPPORT
.................................................................................. 16
P
OWER AND
G
ROUND
................................................................................................................... 19
PINS ONLY AVAILABLE IN BGA PACKAGE ............................................................................ 21
FUNCTIONAL DESCRIPTION ......................................................................................... 22
M
ASTER
C
LOCK
G
ENERATOR
........................................................................................................ 22
F
IGURE
4. T
WO
I
NPUT
C
LOCK
S
OURCE
.................................................................................................................... 22
F
IGURE
5. O
NE
I
NPUT
C
LOCK
S
OURCE
.................................................................................................................... 22
T
ABLE
1: M
ASTER
C
LOCK
G
ENERATOR
.................................................................................................................... 23
RECEIVER........................................................................................................................ 23
R
ECEIVER
I
NPUT
.......................................................................................................................... 23
R
ECEIVE
M
ONITOR
M
ODE
............................................................................................................. 24
R
ECEIVER
L
OSS OF
S
IGNAL
(RLOS) ............................................................................................. 24
F
IGURE
6. S
IMPLIFIED
D
IAGRAM OF
-15
D
B T1/E1 S
HORT
H
AUL
M
ODE AND
RLOS C
ONDITION
.................................. 24
F
IGURE
7. S
IMPLIFIED
D
IAGRAM OF
-29
D
B T1/E1 G
AIN
M
ODE AND
RLOS C
ONDITION
.............................................. 25
F
IGURE
8. S
IMPLIFIED
D
IAGRAM OF
-36
D
B T1/E1 L
ONG
H
AUL
M
ODE AND
RLOS C
ONDITION
.................................... 25
F
IGURE
9. S
IMPLIFIED
D
IAGRAM OF
E
XTENDED
RLOS
MODE
(E1 O
NLY
) ................................................................... 26
R
ECEIVE
HDB3/B8ZS D
ECODER
.................................................................................................. 26
R
ECOVERED
C
LOCK
(RCLK) S
AMPLING
E
DGE
.............................................................................. 26
F
IGURE
10. R
ECEIVE
C
LOCK AND
O
UTPUT
D
ATA
T
IMING
........................................................................................... 27
J
ITTER
A
TTENUATOR
.................................................................................................................... 27
G
APPED
C
LOCK
(JA M
UST BE
E
NABLED IN THE
T
RANSMIT
P
ATH
) .................................................. 27
T
ABLE
2: M
AXIMUM
G
AP
W
IDTH FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
.............................................................. 27
A
RBITRARY
P
ULSE
G
ENERATOR FOR
T1
AND E
1 ........................................................................... 28
F
IGURE
11. A
RBITRARY
P
ULSE
S
EGMENT
A
SSIGNMENT
............................................................................................ 28
TRANSMITTER ................................................................................................................ 28
D
IGITAL
D
ATA
F
ORMAT
................................................................................................................. 28
T
RANSMIT
C
LOCK
(TCLK) S
AMPLING
E
DGE
.................................................................................. 28
F
IGURE
12. T
RANSMIT
C
LOCK AND
I
NPUT
D
ATA
T
IMING
............................................................................................ 29
T
RANSMIT
HDB3/B8ZS E
NCODER
................................................................................................ 29
T
ABLE
3: E
XAMPLES OF
HDB3 E
NCODING
............................................................................................................... 29
T
ABLE
4: E
XAMPLES OF
B8ZS E
NCODING
................................................................................................................ 29
D
RIVER
F
AILURE
M
ONITOR
(DMO) ............................................................................................... 29
T
RANSMIT
P
ULSE
S
HAPER
& L
INE
B
UILD
O
UT
(LBO)
CIRCUIT
........................................................ 30
T
ABLE
5: R
ECEIVE
E
QUALIZER
C
ONTROL AND
T
RANSMIT
L
INE
B
UILD
-O
UT
S
ETTINGS
................................................. 30
TRANSMIT AND RECEIVE TERMINATIONS ................................................................. 31
RECEIVER (C
HANNELS
0 - 7) ..................................................................................................... 31
Internal Receive Termination Mode ........................................................................................................ 31
I
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