PRELIMINARY
APRIL 2007
XR19L400
REV. P1.0.0
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
GENERAL DESCRIPTION
The XR19L400 (L400) is a highly integrated device that
combines a full-featured single channel Universal
Asynchronous Receiver and Transmitter (UART) and RS-
485 transceivers. The L400 is designed to operate with a
3.3V to 5V power supply. The L400 is fully compliant with
RS-485 Standards.
The L400 operates in four different modes: Active, Partial
Sleep, Full Sleep and Power-Save. Each mode can be
invoked via hardware or software. Upon power-up, the
L400 is in the Active mode where the UART and RS-485
transceiver function normally. In the Partial Sleep mode, the
internal crystal oscillator of the UART or charge pump of the
RS-485 transceiver is turned off. In Full Sleep mode, both
the crystal oscillator and the charge pump are turned off.
While the UART is in the Sleep mode, the Power-Save
mode isolates the core logic from the control signals (chip
select, read/write strobes, address and data bus lines) to
minimize the power consumption. The RS-485 receivers
remain active in any of these four modes.
APPLICATIONS
•
Battery-Powered Equipment
•
Handheld and Mobile Devices
•
Handheld Terminals
•
Industrial Peripheral Interfaces
•
Point-of-Sale (POS) Systems
FEATURES
•
Meets
true RS-485 Standards from +3.0V to +5.5V
operation
•
Up to 8 Mbps data transmission rate
•
45us sleep mode exit (charge pump to full power)
•
ESD protection for RS-485 I/O pins at
■
■
■
+/-15kV - Human Body Model
+/- 8kV - IEC 61000-4-2, Contact Discharge
+/- 15kV - IEC 61000-4-2, Air-Gap Discharge
•
Software compatible with industry standard 16550 UART
•
Intel/Motorola bus select
•
Complete modem interface
•
Sleep and Power-save modes to conserve battery power
•
Wake-up interrupt upon exiting low power modes
F
IGURE
1. B
LOCK
D
IAGRAM
VCC33
XTAL1
XTAL2
R_EN
GND
VCC50
ACP
C1+
*5 V Tolerant
Inputs
Intel or Motorola Bus Interface
PwrSave
A2:A0
D7:D0
IOR#
IOW# (R/W#)
CS# (CS#)
INT (IRQ#)
RESET (RESET#)
I/M#
HALF/FULL#
Crystal
Osc/Buffer
BRG
Charge Pump
TX+
TX-
RX+
RX-
VCC33
64 Byte
TX FIFO
UART Registers
64 Byte
RX FIFO
TX
RX
CTS#
Modem
I/Os
DSR#
RI#
CD#
RS-485 Transceiver
XR19L400
UART
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
C1-
XR19L400
PRELIMINARY
REV. P1.0.0
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
F
IGURE
2. P
IN
O
UT OF THE
D
EVICE
40 A1
39 A2
38 INTA
37 NC
36 NC
35 GND
34 HALF/FULLA#
33 VDD50
32 TXA+
31 GND
30 TXA-
29 NC
28 RXA+
27 RXA-
26 C1-
25 C1+
24 NC
23 NC
22 NC
21 VCC33
A0 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
CSA# 10
POWERSAVE 11
XTAL1 12
XTAL2 13
IOW# 14
IOR# 15
NC 16
I/M# 17
RESET 18
ACP 19
R_EN 20
VCC
XR19L400
40- pin QFN
Intel Bus Mode
40 A1
39 A2
38 INTA
37 NC
36 NC
35 GND
34 HALF/FULLA#
33 VDD50
32 TXA+
31 GND
30 TXA-
29 NC
28 RXA+
27 RXA-
26 C1-
25 C1+
24 NC
23 NC
22 NC
21 VCC33
A0 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
CSA# 10
XR19L400
40- pin QFN
Motorola Bus Mode
ORDERING INFORMATION
P
ART
N
UMBER
XR19L400IL40
P
ACKAGE
40-pin QFN
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
D
EVICE
S
TATUS
Active
2
POWERSAVE 11
XTAL1 12
XTAL2 13
IOW# 14
IOR# 15
NC 16
I/M# 17
RESET 18
ACP 19
R_EN 20
GND
PRELIMINARY
REV. P1.0.0
XR19L400
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
PIN DESCRIPTIONS
Pin Descriptions
N
AME
40-QFN
PIN#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE (CMOS/TTL Voltage Levels)
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(NC)
39
40
1
9
8
7
6
5
4
3
2
15
I
Address bus lines [2:0]. These 3 address lines select one of the internal registers in the
UART during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
When I/M# pin is HIGH, the Intel bus interface is selected and this input becomes read
strobe (active LOW). The falling edge instigates an internal read cycle and retrieves the
data byte from an internal register pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on the rising edge.
When I/M# pin is LOW, the Motorola bus interface is selected and this input is not used.
When I/M# pin is HIGH, it selects Intel bus interface and this input becomes write strobe
(active LOW). The falling edge instigates the internal write cycle and the rising edge trans-
fers the data byte on the data bus to an internal register pointed by the address lines.
When I/M# pin is LOW, the Motorola bus interface is selected and this input becomes read
(HIGH) and write (LOW) signal.
When I/M# pin is HIGH, this input is chip select A (active low) to enable channel A in the
device.
When I/M# pin is LOW, this input becomes the chip select (active low) for the Motorola bus
interface.
IOW#
(R/W#)
14
I
CSA#
(CS#)
10
I
INTA
(IRQ#)
38
O When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
(OD) HIGH device interrupt output for channel A. This output is enabled through the software set-
ting of MCR[3]: set to the active mode when MCR[3] is set to a logic 1, and set to the three
state mode when MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output becomes the active
LOW, open-drain interrupt output for both channels. An external pull-up resistor is required
for proper operation. MCR[3] must be set to a logic 0 for proper operation of the interrupt.
SERIAL I/O INTERFACE (RS-485/RS-485 Voltage Levels)
TX+
TX-
RX+
RX-
32
30
28
27
O
I
Differential UART Transmit Data.
Differential UART Receive Data.
ANCILLARY SIGNALS (CMOS/TTL Voltage Levels)
HALF/
FULL#
XTAL1
34
12
I
I
When HALF/FULL# is HIGH, half-duplex mode is enabled.
When HALF/FULL# is LOW, full-duplex mode is enabled.
Crystal or external clock input.
3
XR19L400
Pin Descriptions
N
AME
XTAL2
PwrSave
ACP
I/M#
40-QFN
PIN#
13
11
19
17
T
YPE
O
I
I
I
PRELIMINARY
REV. P1.0.0
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
D
ESCRIPTION
Crystal or buffered clock output.
Power-Save (active high). This feature isolates the L400’s data bus interface from the host
preventing other bus activities that cause higher power drain during sleep mode.
Autosleep for Charge Pump (active HIGH). When this pin is HIGH, the charge pump is shut
off if the UART is already in sleep mode, i.e. the XTAL2 output is LOW.
Intel or Motorola Bus Select.
When I/M# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of
interface.
When I/M# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus
type of interface.
When I/M# pin is HIGH for Intel bus interface, this input becomes RESET (active high).
When I/M# pin is LOW for Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of
the UART. The UART transmitter output will be held HIGH, the receiver input will be ignored
and outputs are reset during reset period.
Charge pump capacitors. As shown in
Figure 1
, a 0.22 uF capacitor should be placed
between these 2 pins.
When the supply voltage is < 3.6V, connect R_EN to GND.
When the supply voltage is > 3.6V, connect R_EN to VCC.
RESET
(RESET#)
18
I
C1+
C1-
R_EN
VCC33
25
26
20
21
-
I
Pwr 3.3V power supply. When VCC33 is used, R_EN pin should be connected to GND and
VCC50 should be left unconnected. A 0.1 uF capacitor to GND is recommended on this
power supply pin. All CMOS/TTL input pins, except XTAL1, are 5V tolerant.
Pwr 5.0V power supply. When VCC50 is used, R_EN pin should be connected to VCC and
VCC33 should be left unconnected. A 1 uF capacitor to GND is recommended on this
power supply pin. All CMOS/TTL input pins, except XTAL1, are 5V tolerant.
Pwr Power supply common, ground.
Pwr The center pad on the backside of the 64-QFN package is metallic and is not electrically
connected to anything inside the device. It must be soldered on to the PCB and may be
optionally connected to GND on the PCB. The thermal pad size on the PCB should be the
approximate size of this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
-
No Connect. Note that in Motorola mode, the IOR# pin also becomes an NC pin.
VCC50
33
GND
-
31, 35
PAD
NC
16, 22, 23,
24, 29, 36,
37
N
OTE
:
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
For CMOS/TTL Voltage levels, ’LOW’
indicates a voltage in the range 0V to VIL and ’HIGH" indicates a voltage in the range VIH to VCC.
4
PRELIMINARY
REV. P1.0.0
XR19L400
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
1.0 PRODUCT DESCRIPTION
The XR19L400 consists of a single channel UART and RS-485 transceivers. It operates from a single +3V to
5.5V supply with data rates up to 8Mbps, while meeting all EIA/TIA-485 specifications. Its feature set is fully
compatible to the XR16V2751 device. Unlike the XR16V2751, most of the modem signals are not CMOS/TTL
level, but conform to RS-485 voltage levels. The configuration register set is 16550 UART compatible for
control, status and data transfer. Also, the L400 has 64-bytes of transmit and receive FIFOs, automatic RTS/
CTS hardware flow control, automatic Xon/Xoff and special character software flow control, transmit and
receive FIFO trigger levels, and a programmable fractional baud rate generator with a prescaler of divide by 1
or 4. Additionally, the L400 includes the ACP pin which the user can shut down the charge pump for the RS-
485 drivers. In the UART portion, the Power-Save feature isolates the databus interface to further reduce
power consumption in the Sleep mode. The L400 is fabricated using an advanced CMOS process.
Enhanced Features
The L400 UART provides a solution that supports 64 bytes of transmit and receive FIFO. Increased
performance is realized in the L400 by the transmit and receive FIFOs, FIFO trigger level controls and
automatic flow control mechanism. This allows the external processor to handle more networking tasks within
a given time. This increases the service interval giving the external CPU additional time for other applications
and reducing the overall UART interrupt servicing time. In addition, the L400 provides the ACP and Power-
Save modes that drastically reduces the power consumption when the device is not used. The combination of
the above greatly reduces the CPU’s bandwidth requirement, increases performance, and reduces power
consumption.
Intel or Motorola Data Bus Interface
The L400 provides a host interface that supports Intel or Motorola microprocessor (CPU) data bus interface.
The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#,
IOW# and CS# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#
and CS# signals for data bus transactions. See pin description section for details on all the control signals. The
Intel and Motorola bus interface selection is made through the pin, I/M#.
Data Rate
The L400 is capable of operation up to 8 Mbps data rate. The device can operate either with a crystal on pins
XTAL1 and XTAL2, or external clock source on XTAL1 pin.
Internal Enhanced Register Sets
The L400 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/
disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/
software flow control enable/disable, programmable baud rates, modem interface controls and status, sleep
mode and infrared mode are all standard features. Following a power on reset or an external reset (and
operating in 16 or Intel Mode), the registers default to the reset condition and is compatible with the
XR16V2751.
RS-485 Interface
The L402 includes RS-485 drivers/receivers for the interface. This feature eliminates the need for an external
RS-485 transceiver. The RS-485 transceiver can be selected to operate in either the half-duplex or full-duplex
mode via the HALF/FULL# pin. The RS-485 drivers guarantee a data rate of up to 8 Mbps.
All RS-485 drivers and receivers are protected to ±15kV using the Human Body Model ground combination,
±8kV using IEC 61000-4-2 Contact Discharge, and ±15kV using IEC 61000-4-2 Air-Gap Discharge. For more
information, send an e-mail to uarttechsupport@exar.com.
5
京公网安备 11010802033920号
EEWORLD
