xr
JANAUARY 2005
PRELIMINARY
XRK79892
REV. P1.0.1
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
phase/frequency alignment will occur with minimal
output phase disturbance. The typical phase bump
caused by a failed clock is eliminated.
FEATURES
GENERAL DESCRIPTION
The XRK79892 is a PLL clock driver designed
specifically for redundant clock tree designs. The
device receives two differential LVPECL clock signals
from which it generates 5 new differential LVPECL
clock outputs. Two of the output pairs regenerate the
input signals frequency and phase while the other
three pairs generate 4x, phase aligned clock outputs.
External PLL feedback is used to also provide zero
delay buffer performance.
The XRK79892 Intelligent Dynamic Clock Switch
circuit continuously monitors both input CLK signals.
Upon detection of a failure (CLK stuck HIGH or LOW
for at least 1 period), the INP_BAD for that CLK will
be latched (H). If that CLK is the primary clock, the
device will switch to the good secondary clock and
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRK79892
•
Fully Integrated PLL
•
Intelligent Dynamic Clock Switch
•
LVPECL Clock Outputs
•
LVCMOS Control I/O
•
3.3V Operation
•
32-Lead LQFP Packagin
•
Pin compatible with MPC9892i
CLK_Selected
INP1Bad
INP0Bad
Man_Override
Alarm_Reset
Sel_CLK
Dynamic
Switch
Logic
PLL_En
Qb0
Qb0
Qb1
Qb1
÷4
Qb2
Qb2
Qa0
Qa0
Qa1
Qa1
OR
CLK0
CLK0
CLK1
CLK1
Ext_FB
Ext_FB
MR
PLL
800-1600MHz
÷16
PRODUCT ORDERING INFORMATION
P
RODUCT
N
UMBER
XRK79892IQ
P
ACKAGE
T
YPE
32-Lead LQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
xr
REV. P1.0.1
XRK79892
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
PRELIMINARY
F
IGURE
2. P
IN
O
UT OF THE
XRK79892
VCC
24
23
22
21
20
19
18
Qa1
Qa1
Qa0
Qa0
VCC
VCC_PLL
Man_Override
PLL_En
17
VCC
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
16
15
14
VCC
Inp0bad
Inp1bad
CK_Selected
GND
Ext_FB
Ext_FB
GND
XRK79892
13
12
11
10
9
Alarm_Reset
Sel_CLK
CLK0
CLK0
CLK1
2
CLK1
GND
MR
XRK79892
PRELIMINARY
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
xr
REV. P1.0.1
PIN DESCRIPTIONS
P
IN
N
AME
CLK0, CLK0
CLK1, CLK1
Ext_FB, Ext_FB
Qa[1:0], Qa[1:0]
Qb[2:0], Qb[2:0]
Inp0bad
T
YPE
LVPECL Input
LVPECL Input
LVPECL Input
LVPECL Output
LVPECL Output
LVCMOS Output
D
ESCRIPTION
Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)
Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)
Differential 1x output pairs
Differential 4x output pairs
Indicates detection of a bad input reference clock 0 with respect to the feed-
back signal. The output is active HIGH and will remain HIGH until the alarm
reset is asserted.
Indicates detection of a bad input reference clock 1 with respect to the feed-
back signal. The output is active HIGH and will remain HIGH until the alarm
reset is asserted.
0 - if clock 0 is selected
1 - if clock 1 is selected
0 - will reset the input bad flags and align Clk_Selected with Sel_Clk. The input
is one-shotted (50KΩ pullup).
0 - selects CLK0
1 - selects CLK1 (40kΩ pulldown)
1 - disables internal clock switch circuitry (40KΩ pulldown).
0 - bypasses selected input reference around the phase-locked loop (50KΩ
pullup).
0 - resets the internal dividers forcing Q outputs LOW. Asynchronous to the
clock (50KΩ pullup).
PLL power supply
Digital power supply
PLL Ground
Digital Ground
Inp1bad
LVCMOS Output
Clk_Selected
Alarm_Reset
Sel_Clk
Manual_Override
PLL_En
MR
VCCA
VCC
GNDA
GND
LVCMOS Output
LVCMOS Input
LVCMOS Input
LVCMOS Input
LVCMOS Input
LVCMOS Input
Power Supply
Power Supply
Power Supply
Power Supply
3
xr
REV. P1.0.1
XRK79892
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
a
S
YMBOL
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
-65
CHARACTERISTICS
M
IN
-0.3
-0.3
-0.3
M
AX
3.6
V
CC
+0.3
V
CC
+0.3
+20
+50
125
U
NIT
V
V
V
mA
mA
°C
C
ONDITION
a.
Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional
operation at absolute-maximum-rated conditions is not implied.
GENERAL SPECIFICATIONS
S
YMBOL
V
TT
MM
HBM
LU
C
IN
θ
JA
C
HARACTERISTICS
Output termination voltage
ESD Protection (Machine model)
ESD Protection (Human body model)
Latch-up immunity
Input Capacitance
Thermal resistance junction to ambient
JESD 51-3, single layer test board
JESD 51-6, multilayer test board
θ
JC
Thermal resistance junction to case
Operating junction temperature
200
2000
200
4.0
M
IN
T
YP
V
CC
-2
M
AX
U
NIT
V
V
V
mA
pF
Inputs
C
ONDITION
62.0
47.0
14
115
°C/W
°C/W
°C/W
°C
Natural convection
Natural convection
4
XRK79892
PRELIMINARY
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
DC C
HARACTERISTICS
(V
CC
= 3.3 + 5%, T
A
= -40
°
C
TO
+85
°
C)
S
YMBOL
C
HARACTERISTICS
M
IN
T
YP
M
AX
U
NIT
xr
REV. P1.0.1
C
ONDITION
LVCMOS control inputs (MR, PLL_En, Sel_CLK, Man_Override, Alarm_Reset)
V
IH
V
IL
I
IN
Input voltage high
Input voltage low
Input current
a
100
2.0
VCC+0.3
0.8
-150
V
V
µΑ
V
IN
=V
CC
or V
IN
=GND
LVCMOS Control Outputs
V
OH
V
OL
Output High Voltage
Output Low Voltage
2.0
0.55
V
V
I
OH
=-10mA
I
OL
=10mA
LVPECL clock inputs (CLK, CLK)
b
I
IN
Input current
+100
µΑ
V
IN
=V
CC
or V
IN
=GND
LVPECL clock outputs (Qa[1:0], Qa[1:0], Qb[2:0], Qb[2:0])
V
OH
V
OL
Output high voltage
Output low voltage
V
CC
-1.2
V
CC
-1.9
V
CC
-0.7
V
CC
-1.45
V
V
Termination 50Ω to V
TT
Termination 50Ω to V
TT
Supply Current
I
GND
I
CCPLL
Maximum ground supply current - gnd pins
Maximum PLL power supply - VCC_PLL pin
180
15
mA
mA
GND pins
V
CCPLL
pin
a.
Inputs have internal pullup/pulldown resistors which affect the input current.
b.
Clock inputs driven by LVPECL compatible signals.
5
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