874003AG-02T datasheet, PDF - EEWORLD Datasheet

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874003AG-02T: DescriptionPLL Based Clock Driver, 874003 Series, 3 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20; Categorylogic logic; File Size701KB，15 Pages; ManufacturerIDT (Integrated Device Technology)

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874003AG-02T Overview

PLL Based Clock Driver, 874003 Series, 3 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20

874003AG-02T Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20
Contacts	20
Reach Compliance Code	not_compliant
ECCN code	EAR99
series	874003
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	6.5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	20
Actual output times	3
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.145 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm
minfmax	98 MHz
Base Number Matches	1

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PCI EXPRESS™ Jitter Attenuator

ICS874003-02

DATA SHEET

General Description

The ICS874003-02 is a high performance Differential-to- LVDS Jitter

Attenuator designed for use in PCI Express systems. In some PCI

Express systems, such as those found in desktop PCs, the PCI

Express clocks are generated from a low bandwidth, high phase

noise PLL frequency synthesizer. In these systems, a jitter

attenuator may be required to attenuate high frequency random and

deterministic jitter components from the PLL synthesizer and from

the system board. The ICS874003-02 has a bandwidth of 400kHz

which is designed to provide good jitter attenuation.

The ICS874003-02 uses IDT’s 3

Generation Femtoclock

PLL

technology to achieve the lowest possible phase noise. The device is

packaged in a 20 lead TSSOP package, making it ideal for use in

space constrained applications such as PCI Express add-in cards.

Features

•

Three differential LVDS output pairs

One differential clock input

CLK, nCLK supports the following input levels: LVPECL, LVDS,

LVHSTL, HCSL, SSTL

Input frequency range: 98MHz to 128MHz

Output frequency range: 98MHz to 320MHz

VCO range: 490MHz - 640MHz

Cycle-to-cycle jitter: 35ps (maximum)

For PCI Express Spread Spectrum Clocking support use the

ICS874003-05

Full 3.3V supply mode

0°C to 70°C ambient operating temperature

Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

F_SEL[2:0] Function Table

Inputs

F_SEL2

F_SEL1

F_SEL0

Outputs

QA[0:1], nQA[0:1]

÷2

÷5

÷4

÷2

÷5

÷4

QB0, nQB0

÷2

÷4

÷5

÷4

÷5

÷4

Pin Assignment

QA1

DDO

QA0

nQA0

F_SEL0

DDA

F_SEL1

nQA1

DDO

QB0

nQB0

F_SEL2

OEB

GND

nCLK

CLK

OEA

ICS874003-02

20-Lead TSSOP

6.5mm x 4.4mm x 0.925mm package body

G Package

Top View

ICS874003AG-02 REVISION B SEPTEMBER 14, 2010

874003AG-02T Related Products

	874003AG-02T	874003AG-02
Description	PLL Based Clock Driver, 874003 Series, 3 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20	PLL Based Clock Driver, 874003 Series, 3 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TSSOP	TSSOP
package instruction	6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20	6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20
Contacts	20	20
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
series	874003	874003
Input adjustment	DIFFERENTIAL	DIFFERENTIAL
JESD-30 code	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e0	e0
length	6.5 mm	6.5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1	1
Number of functions	1	1
Number of terminals	20	20
Actual output times	3	3
Maximum operating temperature	70 °C	70 °C
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225	225
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.145 ns	0.145 ns
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	30
width	4.4 mm	4.4 mm
minfmax	98 MHz	98 MHz
Base Number Matches	1	1

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