Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V
LVPECL Fanout Buffer
ICS8535I-01
G
ENERAL
D
ESCRIPTION
The ICS8535I-01 is a low skew, high performance 1-to-4
LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The
ICS8535I-01 has two single ended clock inputs. the single
ended clock input accepts LVCMOS or LVTTL input levels
and translate them to 3.3V LVPECL levels. The clock
enable is internally synchronized to eliminate runt clock
pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535I-01 ideal for those applications demand-
ing well defined performance and repeatability.
F
EATURES
•
Four differential 3.3V LVPECL outputs
•
Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
•
CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 266MHz
•
Translates LVCMOS and LVTTL levels to
3.3V LVPECL levels
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Propagation delay: 1.9ns (maximum)
•
Jitter, RMS: < 0.09ps (typical)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
CLK0
CLK1
0
1
Q0
nQ0
Q1
nQ1
CLK_SEL
Q2
nQ2
Q3
nQ3
P
IN
A
SSIGNMENT
V
EE
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
ICS8535I-01
20-Lead TSSOP
4.4mm x 6.5mm x 0.92mm body package
G Package
Top View
8535AGI-01
www.idt.com
1
REV. F MAY 28, 2013
Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V
LVPECL Fanout Buffer
ICS8535I-01
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
6
5, 7, 8, 9
10, 13, 18
11, 12
14, 15
16, 17
19, 20
NOTE:
Pullup
Name
V
EE
CLK_EN
CLK_SEL
CLK0
CLK1
nc
V
CC
Power
Input
Input
Input
Input
Unused
Power
Type
Description
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
Pullup
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1 input.
Pulldown
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
Pulldown LVCMOS / LVTTL clock input.
Pulldown LVCMOS / LVTTL clock input.
No connect.
Positive supply pins.
nQ3, Q3
Output
Differential output pair. LVPECL interface levels.
nQ2, Q2
Output
Differential output pair. LVPECL interface levels.
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
nQ0, Q0
Output
Differential output pair. LVPECL interface levels.
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
8535AGI-01
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2
REV. F MAY 28, 2013
Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V
LVPECL Fanout Buffer
ICS8535I-01
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
CLK_SEL
0
1
0
Selected Source
CLK0
CLK1
CLK0
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
Outputs
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
CLK1
Enabled
Enabled
1
1
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as show in Figure 1. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described
in Table 3B.
Disabled
Enabled
CLK0, CLK1
CLK_EN
nQ0:nQ3
Q0:Q3
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK0 or CLK1
0
1
Q0:Q3
LOW
HIGH
Outputs
nQ0:nQ3
HIGH
LOW
8535AGI-01
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3
REV. F MAY 28, 2013
Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V
LVPECL Fanout Buffer
ICS8535I-01
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
73.2°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
55
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK0, CLK1
CLK_EN, CLK_SEL
CLK0, CLK1
CLK_EN, CLK_SEL
CLK0, CLK1, CLK_SEL
CLK_EN
CLK0, CLK1, CLK_SEL
CLK_EN
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-5
-150
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
1.3
0.8
150
5
Units
V
V
V
V
µA
µA
µA
µA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0. 6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
8535AGI-01
www.idt.com
4
REV. F MAY 28, 2013
Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V
LVPECL Fanout Buffer
ICS8535I-01
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
IJ 266MHz
1.0
Test Conditions
Minimum
Typical
Maximum
266
1.9
30
250
0.09
20% to 80% @ 50MHz
30 0
700
Units
MHz
ns
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
jit
t
R
/ t
F
odc
Output Duty Cycle
48
50
52
All parameters measured at 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the V
CC
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8535AGI-01
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5
REV. F MAY 28, 2013
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