1-to-10 Low Skew,
1, 2
LVCMOS/LVTTL
2.5V, 3.3V Fanout Buffer
87946I-147
Datasheet
General Description
The 87946I-147 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Fanout
Buffer. The 87946I-147 has two selectable single ended clock inputs.
The single ended clock inputs accept LVCMOS or LVTTL input
levels. The low impedance LVCMOS/LVTTL outputs are designed to
drive 50 series or parallel terminated transmission lines. The
effective fanout can be increased from 10 to 20 by utilizing the ability
of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of
each bank. The outputs can be utilized in the ÷1, ÷2 or a combination
of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the
internal frequency dividers and also controls the active and high
impedance states of all outputs.
The 87946I-147 is characterized at full 3.3V for input V
DD,
and mixed
3.3V and 2.5V for output operating supply mode. Guaranteed bank,
output and part-to-part skew characteristics make the 87946I-147
ideal for those clock distribution applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
Ten single ended LVCMOS/LVTTL outputs,
7 typical output impedance
Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
Maximum input frequency: 250MHz
Bank skew: 30ps (maximum)
Output skew: 175ps (maximum)
Part-to-part skew: 850ps (maximum)
Multiple frequency skew: 200ps (maximum)
3.3V core, 3.3V or 2.5V output supply modes
-40°C to 85°C ambient operating temperature
Lead-free packaging
Block Diagram
CLK_SEL
Pulldown
CLK0
Pullup
Pullup
CLK1
Pullup
Pin Assignment
MR/nOE
GND
GND
V
DDA
V
DDA
QA0
QA1
QA2
0
1
÷1
÷2
0
1
3
QA[0:2]
CLK_SEL
V
DD
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9
10 11 12 13 14 15 16
QC2
GND
QC0
GND
QC1
V
DDC
QC3
V
DDC
GND
QB0
V
DDB
QB1
GND
QB2
V
DDB
V
DDC
DIV_SELA
Pulldown
0
1
DIV_SELB
Pulldown
0
1
DIV_SELC
Pulldown
MR/nOE
Pulldown
3
CLK0
CLK1
QB[0:2]
DIV_SELA
DIV_SELB
DIV_SELC
GND
4
QC[0:3]
87946I-147
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc.
1
Revision C, September 19, 2016
87946I-147 Datasheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3, 4
5
6
7
8, 11, 15, 20,
24, 27, 31
9, 13, 17
10, 12,
14, 16
18, 22
19,
21, 23
25, 29
26,
28, 30
Name
CLK_SEL
V
DD
CLK0, CLK1
DIV_SELA
DIV_SELB
DIV_SELC
GND
V
DDC
QC0, QC1,
QC2, QC3
V
DDB
QB2,
QB1, QB0
V
DDA
QA2,
QA1, QA0
Input
Power
Input
Input
Input
Input
Power
Power
Output
Power
Output
Power
Output
Pullup
Pulldown
Pulldown
Pulldown
Type
Pulldown
Description
Clock select input. When HIGH, selects CLK1.
When LOW, selects CLK0. LVCMOS / LVTTL interface levels.
Positive supply pin.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Controls frequency division for Bank A outputs. See Table 3
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank B outputs. See Table 3.
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank C outputs. See Table 3.
LVCMOS/LVTTL interface levels.
Power supply ground.
Output supply pins for Bank C outputs.
Single-ended Bank C clock outputs. LVCMOS/LVTTL interface levels.
7 typical output impedance.
Output supply pins for Bank B outputs.
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
7 typical output impedance.
Output supply pins for Bank A outputs.
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
7 typical output impedance.
Active HIGH Master Reset. Active LOW Output Enable. When logic HIGH,
the internal dividers are reset and the outputs are (High-Impedance). When
logic LOW, the internal dividers and the outputs are enabled. See Table 3.
LVCMOS/LVTTL interface levels.
32
MR/nOE
Input
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance V
DD
= V
DDA
= V
DDB
= V
DDC
= 3.6V
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
25
51
51
7
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
pF
k
k
©2016 Integrated Device Technology, Inc.
2
Revision C, September 19, 2016
87946I-147 Datasheet
Function Tables
Table 3. Clock Input Function Table
Inputs
MR/nOE
1
0
0
0
0
0
0
DIV_SELA
X
0
1
X
X
X
X
DIV_SELB
X
X
X
0
1
X
X
DIV_SELC
X
X
X
X
X
0
1
QA0:QA2
High-Impedance
f
IN
/1
f
IN
/2
Active
Active
Active
Active
Outputs
QB0:QB2
High-Impedance
Active
Active
f
IN
/1
f
IN
/2
Active
Active
QC0:QC3
High-Impedance
Active
Active
Active
Active
f
IN
/1
f
IN
/2
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Junction Temperature
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDX
+ 0.5V
47.9C/W (0 lfpm)
-65C to 150C
125°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDA
= V
DDB
= V
DDC
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA,
V
DDB,
V
DDC
I
DD
I
DDA
, I
DDB
, I
DDC
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
Maximum
3.6
3.6
55
23
Units
V
V
mA
mA
©2016 Integrated Device Technology, Inc.
3
Revision C, September 19, 2016
87946I-147 Datasheet
Table 4B. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDA
= V
DDB
= V
DDC
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA,
V
DDB,
V
DDC
I
DD
I
DDA
, I
DDB
, I
DDC
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
55
22
Units
V
V
mA
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDA
= V
DDB
= V
DDC
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Input
Low
Voltage
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
CLK0, CLK1
Input
High
Current
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
CLK0, CLK1
Input
Low
Current
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
CLK0, CLK1
V
OH
V
OL
I
OZL
I
OZH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Hi-Z Current Low
Output Hi-Z Current High
V
DD
= V
IN
= 3.6V
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V, V
IN
= 0V
V
DDA
= V
DDB
= V
DDC
= 3.6V
V
DDA
= V
DDB
= V
DDC
= 3.63V
V
DDA
= V
DDB
= V
DDC
= 3.63V
V
DDA
= V
DDB
= V
DDC
= 3.63V
-5
5
-5
-150
2.6
0.5
Test Conditions
Minimum
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
1.3
150
5
Units
V
V
V
µA
µA
µA
µA
V
V
µA
µA
V
IL
I
IH
I
IL
NOTE 1: Outputs terminated with 50 to V
DDx
/2. See Parameter Measurement Information section.
Load Test Circuit diagrams.
©2016 Integrated Device Technology, Inc.
4
Revision C, September 19, 2016
87946I-147 Datasheet
Table 4D. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDA
= V
DDB
= V
DDC
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Input
Low
Voltage
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
CLK0, CLK1
Input
High
Current
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
CLK0, CLK1
Input
Low
Current
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
CLK0, CLK1
V
OH
V
OL
I
OZL
I
OZH
Output High Voltage;
NOTE 1
Output Low Voltage; NOTE 1
Output Hi-Z Current Low
Output Hi-Z Current High
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DDA
= V
DDB
= V
DDC
= 2.625V
V
DDA
= V
DDB
= V
DDC
= 2.625V
V
DDA
= V
DDB
= V
DDC
= 2.625V
V
DDA
= V
DDB
= V
DDC
= 2.625V
-5
5
-5
-150
1.8
0.5
Test Conditions
Minimum
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
1.3
150
5
Units
V
V
V
µA
µA
µA
µA
V
V
µA
µA
V
IL
I
IH
I
IL
NOTE 1: Outputs terminated with 50 to V
DDx
/2. See Parameter Measurement Information section.
Load Test Circuit diagrams.
©2016 Integrated Device Technology, Inc.
5
Revision C, September 19, 2016
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