874S02BMILFT datasheet, PDF - EEWORLD Datasheet

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874S02BMILFT: DescriptionSOIC-20, Reel; CategoryThe embedded processor and controller Microcontrollers and processors; File Size563KB，18 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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874S02BMILFT Overview

SOIC-20, Reel

874S02BMILFT Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	SOP, SOP20,.4
Contacts	20
Manufacturer packaging code	PSG20
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Description	SOIC 300 MIL
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	12.8 mm
Humidity sensitivity level	1
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	1000 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Master clock/crystal nominal frequency	1000 MHz
Maximum seat height	2.65 mm
Maximum slew rate	97 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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1:1 Differential-to-LVDS Zero Delay

Clock Generator

Data Sheet

874S02I

General Description

The 874S02I is a highly versatile 1:1 Differential- to-LVDS Clock

Generator and a member of the family of High Performance Clock

Solutions from IDT. The 874S02I has a fully integrated PLL and

can be configured as a zero delay buffer, multiplier or divider, and

has an output frequency range of 62.5MHz to 1GHz. The

reference divider, feedback divider and output divider are each

programmable, thereby allowing for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external

feedback allows the device to achieve “zero delay” between the

input clock and the output clocks. The PLL_SEL pin can be used

to bypass the PLL for system test and debug purposes. In bypass

mode, the reference clock is routed around the PLL and into the

internal output dividers.

Features

•

One differential LVDS output pair and

one differential feedback output pair

One differential clock input pair

CLK/nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, SSTL

Input frequency range: 62.5MHz to 1GHz

Output frequency range: 62.5MHz to 1GHz

VCO range: 500MHz - 1GHz

External feedback for "zero delay" clock regeneration with

configurable frequencies

Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

Cycle-to-cycle jitter: 35ps (maximum)

Static phase offset: ±100ps

Full 3.3V supply mode

-40°C to 85°C ambient operating temperature

Available in lead-free packages

Block Diagram

PLL_SEL

Pullup

÷1, ÷2, ÷4, ÷8,

÷16, ÷32, ÷64

Pin Assignment

QFB

nQFB

CLK

nCLK

nFB_IN

FB_IN

SEL2

DDO

nQFB

QFB

GND

SEL1

SEL0

PLL_SEL

DDA

SEL3

GND

DDO

CLK

Pulldown

nCLK

Pullup

PLL

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

FB_IN

Pulldown

nFB_IN

Pullup

874S02I

20-Lead SOIC

7.5mm x 12.8mm x 2.3mm package body

M Package

Top View

SEL0

Pulldown

SEL1

Pulldown

SEL2

Pulldown

SEL3

Pulldown

January 26, 2016

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