1:1 Differential-to-LVDS Zero Delay
Clock Generator
General Description
The 8745B-21 is a highly versatile 1:1 LVDS Clock Generator. The
8745B-21 has a fully integrated PLL and can be configured as zero
delay buffer, multiplier or divider, and has an output frequency range
of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider
and Output Divider are each programmable, thereby allowing for the
following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
1:8. The external feedback allows the device to achieve “zero delay”
between the input clock and the output clock. The PLL_SEL pin can
be used to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL and into
the internal output dividers.
8745B-21
DATA SHEET
Features
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One differential LVDS output designed to meet
or exceed the requirements of ANSI TIA/EIA-644
One differential feedback output pair
Differential CLK, nCLK input pair
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 30ps (maximum)
Output skew: 35ps (maximum)
Static phase offset: 25ps ± 125ps
Full 3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PLL_SEL
Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32
,
÷64
CLK
Pulldown
nCLK
Pullup
0
Q
nQ
Pin Assignment
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
V
DDO
nQFB
QFB
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SEL1
SEL0
V
DD
PLL_SEL
V
DDA
SEL3
GND
Q
nQ
V
DDO
1
QFB
nQFB
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
Pulldown
nFB_IN
Pullup
8745B-21
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
8745B-21 Rev D 2/17/15
1
©2015 Integrated Device Technology, Inc.
8745B-21 DATA SHEET
Table 1. Pin Descriptions
Number
1
2
Name
CLK
nCLK
Input
Input
Type
Pulldown
Pullup
Description
Non-inverting differential clock input.
Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true output Q to go low and the inverted output nQ to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Inverting differential feedback input to phase detector for regenerating clocks with
“Zero Delay.”
Non-inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Output supply pins.
Differential feedback output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Analog supply pin.
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels.
Core supply pin.
3
MR
Input
Pulldown
4
5
6, 15,
19, 20
7, 11
8, 9
10, 14
12, 13
16
17
18
nFBIN
FBIN
SEL2, SEL3,
SEL0 SEL1
V
DDO
nQFB/QFB
GND
nQ/Q
V
DDA
PLL_SEL
V
DD
Input
Input
Input
Power
Output
Power
Output
Power
Input
Power
Pullup
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
2
Rev D 2/17/15
8745B-21 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
46.2C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
125
17
59
Units
V
V
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
SEL[0:3], MR
Input High Current
PLL_SEL
SEL[0:3], MR
I
IL
Input Low Current
PLL_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
5
Rev D 2/17/15
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