the single ended clock input accepts LVCMOS or LVTTL input
levels and translate them to 3.3V LVPECL levels. The clock
enable is internally synchronized to eliminate runt clock pulses
on the output during asynchronous assertion/deassertion of
the clock enable pin.
F
EATURES
•
Four differential 3.3V LVPECL outputs
•
Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
•
CLK0 or CLK1 can accept the following input levels: LVCMOS
or LVTTL
•
Maximum output frequency: 266MHz
•
Translates LVCMOS and LVTTL levels to
3.3V LVPECL levels
•
Output skew: TBD
•
Part-to-part skew: TBD
•
Propagation delay: 1.3ns (typical)
•
Additive phase jitter, RMS: 0.04ps (typical)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
IC
S
Guaranteed output and part-to-part skew characteristics make
the ICS8535BI-01 ideal for those applications demanding well
defined performance and repeatability.
P
IN
A
SSIGNMENT
nQ1
Q1
V
CC
nQ0
Q0
V
EE
CLK_EN
CLK_SEL
nc
CLK0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q2
nQ2
V
CC
nc
Q3
nQ3
V
CC
nc
nc
CLK1
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
CLK0
CLK1
0
1
Q0
nQ0
Q1
nQ1
CLK_SEL
Q2
nQ2
V
CC
Q3
nQ3
V
CC
nc
Q3
nQ3
ICS8535BI-01
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm body package
G Package
Top View
nQ1
nQ2
V
CC
Q1
Q2
V
CC
nQ0
Q0
V
EE
CLK_EN
1
2
3
4
5
20 19 18 17 16
15
14
13
12
6
CLK_SEL
7
CLK0
8
nc
9
CLK1
11
10
nc
ICS8535BI-01
20-Lead VFQFN
4mm x 4mm x 0.925mm body package
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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