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7133LA25GGI

Description
Dual-Port SRAM, 2KX16, 25ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-68
Categorystorage    storage   
File Size154KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

7133LA25GGI Overview

Dual-Port SRAM, 2KX16, 25ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-68

7133LA25GGI Parametric

Parameter NameAttribute value
MakerIDT (Integrated Device Technology)
package instructionPGA,
Reach Compliance Codecompliant
Maximum access time25 ns
JESD-30 codeS-CPGA-P68
memory density32768 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Number of functions1
Number of terminals68
word count2048 words
character code2000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize2KX16
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formPIN/PEG
Terminal locationPERPENDICULAR
Base Number Matches1
HIGH SPEED
2K X 16 DUAL-PORT
SRAM
Features
IDT7133SA/LA
IDT7143SA/LA
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
High-speed access
– Military: 35/55/70/90ns (max.)
– Industrial: 25/55ns (max.)
– Commercial: 20/25/35/45/55/70/90ns (max.)
Low-power operation
– IDT7133/43SA
Active: 1150mW (typ.)
Standby: 5mW (typ.)
– IDT7133/43LA
Active: 1050mW (typ.)
Standby: 1mW (typ.)
Versatile control for write: separate write control for lower
and upper byte of each port
MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
On-chip port arbitration logic (IDT7133 only)
BUSY
output flag on IDT7133;
BUSY
input on IDT7143
Fully asynchronous operation from either port
Battery backup operation–2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
LUB
CE
L
R/W
RUB
CE
R
R/W
LLB
OE
L
R/W
RLB
OE
R
I/O
8L
- I/O
15L
I/O
0L
- I/O
7L
BUSY
L
(1)
A
10L
A
0L
ADDRESS
DECODER
11
I/O
CONTROL
I/O
CONTROL
I/O
8R
- I/O
15R
I/O
0R
- I/O
7R
BUSY
R
(1)
MEMORY
ARRAY
ADDRESS
DECODER
11
A
10R
A
0R
CE
L
ARBITRATION
LOGIC
(IDT7133 ONLY)
CE
R
2746 drw 01
NOTE:
1. IDT7133 (MASTER):
BUSY
is open drain output and requires pull-up resistor.
IDT7143 (SLAVE):
BUSY
is input.
JUNE 2018
1
©2018 Integrated Device Technology, Inc.
DSC 2746/15
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