– Programmable baud rate generator derived from the system
clock
– Fully programmable serial characteristics:
– 5, 6, 7, or 8 bit characters
– Even, odd or no parity bit generation and detection
– 1, 1-1/2 or 2 stop bit generation
– Line break generation and detection
– False start bit detection
– Internal loopback mode
x
2
I C-Bus
– Supports standard 100 Kbps mode as well as 400 Kbps fast
mode
– Supports 7-bit and 10-bit addressing
– Supports four modes: master transmitter, master receiver,
slave transmitter, slave receiver
x
Additional General Purpose Peripherals
– Interrupt controller
– System integrity functions
– General purpose I/O controller
– Serial peripheral interface (SPI)
x
Counter/Timers
– Three general purpose 32-bit counter timers
– Timers may be cascaded
– Selectable counter/timer clock source
x
JTAG Interface
– Compatible with IEEE Std. 1149.1 - 1990
x
Core
CPU Execution Core
The 32-bit CPU core is 100% compatible with the MIPS32 instruction
set architecture (ISA). Specifically, this device features the 4Kc CPU
core developed by MIPS Technologies Inc. (www.mips.com). This core
issues a single instruction per cycle, includes a five stage pipeline and is
optimized for applications that require integer arithmetic.
The CPU core includes 8 KB instruction and 8 KB data caches. Both
caches are 4-way set associative and can be locked on a per line basis,
which allows the programmer control over this precious on-chip memory
resource. The core also features a memory management unit (MMU).
The CPU core also incorporates an enhanced joint test access group
(EJTAG) interface that is used to interface to in-circuit emulator tools,
providing access to internal registers and enabling the part to be
controlled externally, simplifying the system debug process.
The use of this core allows IDT's customers to leverage the broad
range of software and development tools available for the MIPS archi-
tecture, including operating systems, compilers, and in-circuit emula-
tors.
PCI Interface
The PCI interface on the RC32434 is compatible with version 2.2 of
the PCI specification. An on-chip arbiter supports up to six external bus
masters, supporting both fixed priority and rotating priority arbitration
schemes. The part can support both satellite and host PCI configura-
tions, enabling the RC32434 to act as a slave controller for a PCI add-in
card application or as the primary PCI controller in the system. The PCI
interface can be operated synchronously or asynchronously to the other
I/O interfaces on the RC32434 device.
Ethernet Interface
The RC32434 has one Ethernet Channel supporting 10Mbps and
100Mbps speeds to provide a standard media independent interface
(MII or RMII), allowing a wide range of external devices to be connected
efficiently.
Double Data Rate Memory Controller
The RC32434 incorporates a high performance double data rate
(DDR) memory controller which supports x16 memory configurations up
to 256MB. This module provides all of the signals required to interface
to discrete memory devices, including a chip select, differential clocking
outputs and data strobes.
I/ Controller
Memory and I/O Controller
The RC32434 uses a dedicated local memory/IO controller including
a de-multiplexed 8-bit data and 26-bit address bus. It includes all of the
signals required to interface directly to a maximum of four Intel or
Motorola-style external peripherals.
2 of 53
January 19, 2006
IDT RC32434
DMA Controller
The DMA controller consists of 6 independent DMA channels, all of
which operate in exactly the same manner. The DMA controller off-loads
the CPU core from moving data among the on-chip interfaces, external
peripherals, and memory. The controller supports scatter/gather DMA
with no alignment restrictions, making it appropriate for communications
and graphics systems.
UART Interface
The RC32434 contains a serial channel (UART) that is compatible
with the industry standard 16550 UART.
I
2
C Interface
The standard I2C interface allows the RC32434 to connect to a
number of standard external peripherals for a more complete system
solution. The RC32434 supports both master and slave operations.
General Purpose I/O Controller
The RC32434 has 14 general purpose input/output pins. Each pin
may be used as an active high or active low level interrupt or non-
maskable interrupt input, and each signal may be used as a bit input or
output port.
System Integrity Functions
The RC32434 contains a programmable watchdog timer that gener-
ates a non-maskable interrupt (NMI) when the counter expires and also
contains an address space monitor that reports errors in response to
accesses to undecoded address regions.
April 19, 2004:
Added the I
2
C feature. In Table 20, pin L1 becomes
SDA and pin L2 becomes SCL.
May 25, 2004:
In Table 9, signals MIIRXCLK and MIITXCLK, the Min
and Max values for Thigh/Tlow_9c were changed to 140 and 260
respectively and the Min and Max values for Thigh/Tlow_9d were
changed to 14.0 and 26.0 respectively.
December 8, 2005:
In Table 18, corrected error for Capacitance Max
value from 8.0 to 10.5.
January 19, 2006:
Removed all references to NVRAM.
Thermal
Thermal Considerations
The RC32434 is guaranteed in an ambient temperature range of 0°
to +70° C for commercial temperature devices and - 40° to +85° for
industrial temperature devices.
History
Revision Histor y
November 3, 2003:
Initial publication. Preliminary Information.
December 15, 2003:
Final version. In Table 7, changed maximum
value for Tskew in 266MHz category and changed values for Tdo in all
speed grades for signals DDRADDR, etc. In Table 8, changed minimum
values in all speed grades for all Tdo signals and for Tsu and Tzd in
MDATA[7:0]. In Table 16, added reference to Power Considerations
document. In Table 17, added 2 rows under PCI and Notes 1 and 2.
January 5, 2004:
In Table 19, Pin F6 was changed from Vcc I/O to
Vss. In Table 23, pin F6 was deleted from the Vcc I/O row and added to
the Vss row.
January 27, 2004:
In Table 3, revised description for MADDR[3:0]
and changed 4096 cycles to 4000 for MADDR[7]. (Note: MADDR was
incorrectly labeled as MDATA in previous data sheet.)
March 29, 2004:
Added Standby mode to Table 16, Power
Consumption.
3 of 53
January 19, 2006
IDT RC32434
Pin Description Table
The following table lists the functions of the pins provided on the RC32434. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
Memory and Peripheral Bus
BDIRN
O
External Buffer Direction.
Controls the direction of the external data bus buffer
for the memory and peripheral bus. If the RC32434 memory and peripheral bus
is connected to the A side of a transceiver, such as an IDT74FCT245, then this
pin may be directly connected to the direction control (e.g., BDIR) pin of the
transceiver.
External Buffer Enable.
This signal provides an output enable control for an
external buffer on the memory and peripheral data bus.
Write Enables.
This signal is the memory and peripheral bus write enable sig-
nal.
Chip Selects.
These signals are used to select an external device on the mem-
ory and peripheral bus.
Address Bus.
22-bit memory and peripheral bus address bus.
MADDR[25:22] are available as GPIO alternate functions.
Data Bus.
8-bit memory and peripheral data bus. During a cold reset, these pins
function as inputs that are used to load the boot configuration vector.
Output Enable.
This signal is asserted when data should be driven by an exter-
nal device on the memory and peripheral bus.
Read Write.
This signal indicates whether the transaction on the memory and
peripheral bus is a read transaction or a write transaction. A high level indicates
a read from an external device. A low level indicates a write to an external
device.
Wait or Transfer Acknowledge.
When configured as wait, this signal is
asserted during a memory and peripheral bus transaction to extend the bus
cycle. When configured as a transfer acknowledge, this signal is asserted during
a transaction to signal the completion of the transaction.
BOEN
WEN
CSN[3:0]
MADDR[21:0]
MDATA[7:0]
OEN
RWN
O
O
O
O
I/O
O
O
WAITACKN
I
DDR Bus
DDRADDR[13:0]
DDRBA[1:0]
DDRCASN
DDRCKE
O
O
O
O
DDR Address Bus.
14-bit multiplexed DDR address bus. This bus is used to
transfer the addresses to the DDR devices.
DDR Bank Address.
These signals are used to transfer the bank address to the
DDRs.
DDR Column Address Strobe.
This signal is asserted during DDR transac-
tions.
DDR Clock Enable.
The DDR clock enable signal is asserted during normal
DDR operation. This signal is negated following a cold reset or during a power
down operation.
DDR Negative DDR clock.
This signal is the negative clock of the differential
DDR clock pair.
Table 1 Pin Description (Part 1 of 6)
DDRCKN
O
4 of 53
January 19, 2006
IDT RC32434
Signal
DDRCKP
DDRCSN
DDRDATA[15:0]
DDRDM[1:0]
Type
O
O
I/O
O
Name/Description
DDR Positive DDR clock.
This signal is the positive clock of the differential
DDR clock pair.
DDR Chip Selects.
This active low signal is used to select DDR device(s) on
the DDR bus.
DDR Data Bus.
16-bit DDR data bus is used to transfer data between the
RC32434 and the DDR devices. Data is transferred on both edges of the clock.
DDR Data Write Enables.
Byte data write enables are used to enable specific
byte lanes during DDR writes.
DDRDM[0] corresponds to DDRDATA[7:0]
DDRDM[1] corresponds to DDRDATA[15:8]
DDR Data Strobes.
DDR byte data strobes are used to clock data between
DDR devices and the RC32434. These strobes are inputs during DDR reads
and outputs during DDR writes.
DDRDQS[0] corresponds to DDRDATA[7:0]
DDRDQS[1] corresponds to DDRDATA[15:8]
DDR Row Address Strobe.
The DDR row address strobe is asserted during
DDR transactions.
DDR Voltage Reference.
SSTL_2 DDR voltage reference is generated by an
external source.
DDR Write Enable.
DDR write enable is asserted during DDR write transac-
tions.
DDRDQS[1:0]
I/O
DDRRASN
DDRVREF
DDRWEN
PCI Bus
PCIAD[31:0]
O
I
O
I/O
PCI Multiplexed Address/Data Bus.
Address is driven by a bus master during
initial PCIFRAMEN assertion. Data is then driven by the bus master during
writes or by the bus target during reads.
PCI Multiplexed Command/Byte Enable Bus.
PCI commands are driven by
the bus master during the initial PCIFRAMEN assertion. Byte enable signals are
driven by the bus master during subsequent data phase(s).
PCI Clock.
Clock used for all PCI bus transactions.
PCI Device Select.
This signal is driven by a bus target to indicate that the tar-
get has decoded the address as one of its own address spaces.
PCI Frame.
Driven by a bus master. Assertion indicates the beginning of a bus
transaction. Negation indicates the last data.
PCI Bus Grant.
In PCI host mode with internal arbiter:
The assertion of these signals indicates to the agent that the internal RC32434
arbiter has granted the agent access to the PCI bus.
In PCI host mode with external arbiter:
PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32434 that
access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
In PCI satellite mode:
PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the
RC32434 that access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
PCI Initiator Ready.
Driven by the bus master to indicate that the current datum
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