3.3 VOLT CMOS DUAL SyncFIFO™
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1,024 x 18, DUAL 2,048 x 18
and DUAL 4,096 x 18
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs
The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs
The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs
The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs
The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs
Offers optimal combination of large capacity (8K), high speed,
design flexibility, and small footprint
Ideal for the following applications:
– Network switching
– Two level prioritization of parallel data
– Bidirectional data transfer
– Bus-matching between 18-bit and 36-bit data paths
– Width expansion to 36-bit per package
– Depth expansion to 8,192 words per package
10 ns read/write cycle time
5V input tolerant
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full Flags
•
•
•
•
•
•
•
•
•
Easily expandable in depth and width
Asynchronous or coincident Read and Write Clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output enable puts output data bus in high-impedance state
High-performance submicron CMOS technology
Available in a 128-pin thin quad flatpack (TQFP)
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide
synchronous (clocked) First-in, First-out (FIFO) memories designed to run
off a 3.3V supply for exceptionally low power consumption. One dual
IDT72V805/72V815/72V825/72V835/72V845 device is functionally equiva-
lent to two IDT72V205/72V215/72V225/72V235/72V245 FIFOs in a single
package with all associated control, data, and flag lines assigned to
independent pins. These devices are very high-speed, low-power First-In,
FUNCTIONAL BLOCK DIAGRAM
FFA/IRA
WCLKA
WENA
HFA/(WXOA)
PAEA
EFA/
ORA
WCLKB
WENB
PAFA
DA
0
-DA
17
LDA
DB0-DB17
LDB
INPUT
REGISTER
OFFSET
REGISTER
INPUT
REGISTER
OFFSET
REGISTER
FFB/IRB
PAFB
EFB/ORB
PAEB
HFB/(WXOB)
WRITE
CONTROL
LOGIC
WRITE
POINTER
FLA
WXIA
(HFA)/WXOA
RXIA
RXOA
RSA
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
FLAG
LOGIC
WRITE
CONTROL
LOGIC
READ
POINTER
READ
CONTROL
LOGIC
WRITE
POINTER
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
FLAG
LOGIC
READ
POINTER
READ
CONTROL
LOGIC
EXPANSION
LOGIC
OUTPUT
REGISTER
EXPANSION
LOGIC
OUTPUT
REGISTER
RESET
LOGIC
RESET
LOGIC
OEA
QA
0
-QA
17
RCLKA
RENA
RSB
RXOB
RXIB
(HFB)/WXOB
WXIB
FLB
OEB
QB
0
-QB
17
RCLKB
RENB
4295 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2009
DSC-4295/4
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
First-Out (FIFO) memories with clocked read and write controls. These FIFOs
are applicable for a wide variety of data buffering needs, such as optical disk
controllers, Local Area Networks (LANs), and interprocessor communication.
Each of the two FIFOs contained in these devices has an 18-bit input and
output port. Each input port is controlled by a free-running clock (WCLK), and
an input enable pin (WEN). Data is read into the synchronous FIFO on every
clock when
WEN
is asserted. The output port of each FIFO bank is controlled
by another clock pin (RCLK) and another enable pin (REN). The Read Clock
can be tied to the Write Clock for single clock operation or the two clocks can
run asynchronous of one another for dual-clock operation. An Output Enable
pin (OE) is provided on the read port of each FIFO for three-state control of
the output.
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
programmable flags is controlled by a simple state machine, and is initiated
by asserting the Load pin (LD). A Half-Full flag (HF) is available for each FIFO
that is implemented as a single device.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard Mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating
REN
and
enabling a rising RCLK edge, will shift the word from internal memory to the
data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or
First Word Fall Through (FWFT) mode. The
XI
and
XO
pins are used to
expand the FIFOs. In depth expansion configuration,
FL
is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V805/72V815/72V825/72V835/72V845 are fabricated using
IDT’s high-speed submicron CMOS technology.
PIN CONFIGURATIONS
INDEX
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
WXIA
WENA
WCLKA
FLA
PAEA
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
DA16
DA17
GND
RCLKA
RENA
QB0
QB1
GND
QB2
QB3
V
CC
QB4
GND
QB5
QB6
QB7
QB8
GND
QB9
QB10
V
CC
QB11
QB12
GND
QB13
QB14
V
CC
QB15
GND
QB16
QB17
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
V
CC
PAFA
RXIA
FFA
WXOA/HFA
RXOA
QA0
QA1
GND
QA2
QA3
V
CC
QA4
GND
QA5
QA6
QA7
QA8
GND
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PAEB
FLB
WCLKB
WENB
WXIB
V
CC
PAFB
RXIB
FFB
WXOB/HFB
RXOB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
LDA
OEA
RSA
V
CC
GND
EFA
QA17
QA16
GND
QA15
V
CC
QA14
QA13
GND
QA12
QA11
V
CC
QA10
QA9
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
GND
RCLKB
RENB
LDB
OEB
RSB
V
CC
GND
EFB
4295 drw 02
TQFP (PK128-1, ORDER CODE: PF)
TOP VIEW
2
FEBRUARY 11, 2009
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
DA
0
–DA
17
RSA
WCLKA
WCLKB
WENA
WENB
RCLKA
RENA
RENB
OEA
LDA
LDB
FLA
FLB
Name
Data Inputs
DB
0
-DB
17
Reset
RSB
Write Clock
Write Enable
Read Clock
RCLKB
Read Enable
Output Enable
OEB
Load
I/O
I
I
I
I
I
I
I
I
Data inputs for an 18-bit bus.
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an initial WRITE after power-up.
When
WEN
is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK.
When
WEN
is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the
FF
is LOW.
When
REN
is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not
empty.
When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When
REN
is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the
EF
is low.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a
high-impedance state.
When
LD
is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when
WEN
is LOW. When
LD
is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when
REN
is LOW.
In the single device or width expansion configuration,
FL
together with
WXI
and
RXI
etermine if the mode is IDT
Standard mode or First Word Fall Through (FWFT) mode, as well as whether the
PAE/PAF
flags are synchronous
or asynchronous. (See Table I.) In the Daisy Chain Depth Expansion configuration,
FL
is grounded on the first
device (first load device) and set to HIGH for all other devices in the Daisy Chain.
In the single device or width expansion configuration,
WXI
together with
FL
and
RXI
Input determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the
PAE/PAF
flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
WXI
is connected to
WXO
(Write Expansion
Out) of the previous device.
In the single device or width expansion configuration,
RXI
together with
FL
and
WXI,
Input determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the
PAE/PAF
flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
RXI
is connected to
RXO
(Read
Expansion Out) of the previous device.
In the IDT Standard mode, the
FF
function is selected.
FF
indicates whether or not the FIFO memory is full.
In the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available for writing to
the FIFO memory.
In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or not the FIFO memory is
empty. In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is valid data available at
the outputs.
When
PAE
is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default offset
at reset is 31 from empty for IDT72V805LB, 63 from empty for IDT72V815LB, and 127 from empty for IDT7V2825LB/
72V835LB/72V845LB.
When
PAF
is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
at reset is 31 from full for IDT72V805LB, 63 from full for IDT72V815LB, and 127 from full for IDT72V825LB/
72V835LB/72V845LB.
In the single device or width expansion configuration, the device is more than half full Out/Half-Full Flag
when
HF
is LOW. In the depth expansion configuration, a pulse is sent from
WXO
to
WXI
of the next device
when the last location in the FIFO is written.
In the depth expansion configuration, a pulse is sent from
RXO
to
RXI
of the next device when the last location
in the FIFO is read.
Data outputs for an 18-bit bus.
+3.3V power supply pins.
Ground pins.
Description
First Load
I
WXIA
WXIB
Write Expansion
I
RXIA
RXIB
Read Expansion
I
FFA/IRA
FFB/IRB
EFA/ORA
EFB/ORB
PAEA
PAEB
PAFA
PAFB
WXOA/HFA
WXOB/HFB
RXOA
RXOB
QA
0
–QA
17
QB
0
-QB
17
V
CC
GND
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost-Empty flag
Programmable
Almost-Full Flag
Write Expansion
O
O
O
O
O
Read Expansion
Out
Data Outputs
Power
Ground
O
O
3
FEBRUARY 11, 2009
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage
with respect to GND
Storage
Temperature
DC Output Current
Commercial
–0.5 to +5
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED OPERATING DC
CONDITIONS
Symbol
Parameter
Supply Voltage
V
CC
Commercial/Industrial
GND
V
IH
V
IL
(1)
Supply Voltage
Input High Voltage
Commercial/Industrial
Input Low Voltage
Commercial/Industrial
Operating Temperature
Commercial
Operating Temperature
Industrial
Min.
3.0
0
2.0
—
0
-40
Typ.
3.3
0
—
—
—
⎯
Max.
3.6
0
5.0
0.8
70
85
Unit
V
V
V
V
°C
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
T
A
T
A
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 3.3V ± 0.3V, T
A
= 0°C to +70°C; Industrial: V
CC
= 3.3V
±
0.3V, TA = -40°C to +85°C)
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
Commercial & Industrial
(1)
t
CLK
= 10, 15, 20 ns
Typ.
—
—
—
—
—
—
Symbol
I
LI
(2)
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Standby Current
Min.
–1
–10
2.4
—
—
—
Max.
1
10
—
0.4
60
10
Unit
µA
µA
V
V
mA
mA
I
LO
(3)
V
OH
V
OL
I
CC1
(4,5,6)
I
CC2
(4,7)
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4
≤
V
IN
≤
V
CC
.
3.
OE
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
4. Tested with outputs disabled (I
OUT
= 0).
5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
6. Typical I
CC1
= 2[2.04 + 0.88*f
S
+ 0.02*C
L
*f
S
] (in mA).
These equations are valid under the following conditions:
V
CC
= 3.3V, T
A
= 25°C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
7. All Inputs = V
CC
–0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
(1)
Input
Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
NOTES:
1. With output deselected, (OE
≥
V
IH
).
2. Characterized values, not currently tested.
4
FEBRUARY 11, 2009
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 3.3V ± 0.3V, T
A
= 0°C to +70°C; Industrial: V
CC
= 3.3V
±
0.3V, TA = -40°C to +85°C)
Commercial
IDT72V805L10
IDT72V815L10
IDT72V825L10
IDT72V835L10
IDT72V845L10
Min.
Max.
100
—
2
6.5
10
—
4.5
—
4.5
—
3
—
0.5
—
3
—
0.5
—
10
—
8
—
8
—
—
15
0
—
—
6
1
6
—
6.5
—
6.5
—
17
—
—
—
—
—
3
3
5
14
8
17
8
17
6.5
—
—
—
—
Com’l & Ind’l
(2)
IDT72V805L15
IDT72V815L15
IDT72V825L15
IDT72V835L15
IDT72V845L15
Min.
Max.
66.7
—
2
10
15
—
6
—
6
—
4
—
1
—
4
—
1
—
15
—
10
—
10
—
—
15
0
—
3
8
3
8
—
10
—
10
—
20
—
—
—
—
—
6.5
5
6
18
10
20
10
20
10
—
—
—
—
Commercial
IDT72V805L20
IDT72V815L20
IDT72V825L20
IDT72V835L20
IDT72V845L20
Min.
Max.
50
MHz
2
12
20
—
8
—
8
—
5
—
1
—
5
—
1
—
20
—
12
—
12
—
—
20
0
—
3
10
3
10
—
12
—
12
—
22
—
—
—
—
—
8
8
8
20
12
22
12
22
12
—
—
—
—
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAFA
t
PAFS
t
PAEA
t
PAES
t
HF
t
XO
t
XI
t
XIS
t
SKEW1
t
SKEW2
(4)
Parameter
Clock Cycle Frequency—
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
(1)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(3)
Output Enable to Output Valid
Output Enable to Output in High-Z
(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Asynchronous Programmable
Almost-Full Flag
Write Clock to Synchronous
Programmable Almost-Full Flag
Clock to Asynchronous Programmable
Almost-Empty Flag
Read Clock to Synchronous
Programmable Almost-Empty Flag
Clock to Half-Full Flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Setup Time
Skew time between Read Clock &
Write Clock for
FF/IR
and
EF/OR
Skew time between Read Clock &
Write Clock for
PAE
and
PAF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Industrial temperature range product for the 15ns speed grade is available as a standard device.
3. Values guaranteed by design, not currently tested.
4. t
SKEW2
applies to synchronous
PAE
and synchronous
PAF
only.
3.3V
330Ω
D.U.T.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
5
510Ω
30pF*
4295 drw 03
Figure 1. Output Load
* Includes jig and scope capacitances.
FEBRUARY 11, 2009
PCB Design
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EEWORLD
