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5962F9659701QCC

Description
NOR Gate, ACT Series, 2-Func, 4-Input, CMOS, CDIP14, CERAMIC, SIDE BRAZED, DIP-14
Categorylogic    logic   
File Size225KB,9 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5962F9659701QCC Overview

NOR Gate, ACT Series, 2-Func, 4-Input, CMOS, CDIP14, CERAMIC, SIDE BRAZED, DIP-14

5962F9659701QCC Parametric

Parameter NameAttribute value
MakerCobham Semiconductor Solutions
Parts packaging codeDIP
package instructionDIP,
Contacts14
Reach Compliance Codeunknown
seriesACT
JESD-30 codeR-CDIP-T14
JESD-609 codee4
Logic integrated circuit typeNOR GATE
Number of functions2
Number of entries4
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)14 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class Q
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose300k Rad(Si) V
width7.62 mm
Base Number Matches1
Standard Products
UT54ACS4002/UT54ACTS4002
Dual 4-Input NOR Gates
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS4002 - SMD 5962-96596
UT54ACTS4002 - SMD 5962-96597
DESCRIPTION
The UT54ACS4002 and the UT54ACTS4002 are dual 4-input
NOR gates. A high on any input forces the output to a low state.
The circuits perform the Boolean functions:
Y = A + B + C + D = A⋅B⋅C⋅D.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
An
L
H
X
X
X
Bn
L
X
H
X
X
Cn
L
X
X
H
X
Dn
L
X
X
X
H
OUTPUT
Yn
H
L
L
L
L
PINOUTS
14-Pin DIP
Top View
Y1
A1
B1
C1
D1
NC
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
Y2
D2
C2
B2
A2
NC
14-Lead Flatpack
Top View
Y1
A1
B1
C1
D1
NC
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
Y2
D2
C2
B2
A2
NC
LOGIC DIAGRAM
LOGIC SYMBOL
A1
B1
C1
D1
A2
B2
C2
D2
Y1
Y2
A1
B1
C1
D1
A2
B2
C2
D2
(2)
(3)
(4)
(5)
(9)
(10)
(11)
(12)
≥1
(1)
Y1
(13)
Y2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
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