CY7C460A/CY7C462A
CY7C464A/CY7C466A
Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 9 FIFO (CY7C460A)
• 16K x 9 FIFO (CY7C462A)
• 32K x 9 FIFO (CY7C464A)
• 64K x 9 FIFO (CY7C466A)
• 10-ns access times, 20-ns read/write cycle times
• High-speed 50-MHz read/write independent of
depth/width
• Low operating power
— I
CC
= 60 mA
•
•
•
•
•
•
•
•
•
•
•
— I
SB
=8 mA
Asynchronous read/write
Empty and Full flags
Half Full flag (in standalone mode)
Retransmit (in standalone mode)
TTL-compatible
Width and Depth Expansion Capability
5V
±
10% supply
PLCC, LCC, 300-mil and 600-mil DIP packaging
Three-state outputs
Pin compatible density upgrade to CY7C42X/46X family
Pin compatible and functionally equivalent to IDT7205,
IDT7206, IDT7207, IDT7208
Functional Description
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are
respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in
first-out (FIFO) memories. Each FIFO memory is organized
such that the data is read in the same sequential order that it
was written. Full and Empty flags are provided to prevent over-
run and underrun. Three additional pins are also provided to
facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one
device to another by passing tokens.
The read and write operations may be asynchronous; each
can occur at a rate of up to 50 MHz. The write operation occurs
when the Write (W) signal is LOW. Read occurs when Read
(R) goes LOW. The nine data outputs go to the high-imped-
ance state when R is HIGH.
A Half Full (HF) output flag is provided that is valid in the stan-
dalone (single device) and width expansion configurations. In
the depth expansion configuration, this pin provides the expan-
sion out (XO) information that is used to tell the next FIFO that
it will be activated.
In the standalone and width expansion configurations, a LOW
on the Retransmit (RT) input causes the FIFOs to retransmit
the data. Read Enable (R) and Write Enable (W) must both be
HIGH during a retransmit cycle, and then R is used to access
the data.
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are
fabricated using Cypress’s advanced 0.5µ RAM3 CMOS tech-
nology. Input ESD protection is greater than 2000V and
latch-up is prevented by careful layout and the use of guard
rings.
Logic Block Diagram
DATAINPUTS
(D
0
−D
8
)
Pin Configurations
PLCC/LCC
Top View
V
cc
D
4
D
5
NC
D
3
D
8
W
DIP
Top View
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
7C460A
23
7C462A
7C464A 22
7C466A
21
20
19
18
17
16
15
W
WRITE
CONTROL
WRITE
POINTER
DUAL PORT
RAM ARRAY
8K x 9
16K x 9
32K x 9
64K x 9
READ
POINTER
D
2
D
1
D
0
XI
FF
Q
0
Q
1
THREE–
STATE
BUFFERS
DATAOUTPUTS
(Q
0
-Q
8
)
NC
Q
2
4
5
6
7
8
9
10
11
12
3
2
1
32 31 30
29
28
27
D
6
D
7
NC
FL/RT
MR
EF
XO/HF
Q
7
Q
6
7C460A
7C462A
7C464A
7C466A
26
25
24
23
22
13
21
14 15 16 17 18 19 20
Q
3
Q
8
GND
NC
R
Q
4
Q
5
R
READ
CONTROL
RESET
LOGIC
MR
FL/RT
C46XA–2
V
CC
D
4
D
5
D
6
D
7
FL/RT
MR
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
C46XA–3
FLAG
LOGIC
EXPANSION
LOGIC
EF
FF
XI
XO/HF
C46XA–1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 4, 1999
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Selection Guide
7C460A-10
7C462A-10
7C464A-10
7C466A-10
Frequency (MHz)
Maximum Access Time (ns)
50
10
7C460A-15
7C462A-15
7C464A-15
7C466A-15
40
15
7C460A-25
7C462A-25
7C464A-25
7C466A-25
28.5
25
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied .............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Power Dissipation .......................................................... 1.0W
Output Current, into Outputs (LOW)............................ 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Military
[1]
Ambient
Temperature
0
°
C to + 70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
[2]
7C460A/462A/464A/466A
(-10,-15,-25)
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
GND < V
I
< V
CC
R > V
IH
, GND < V
O
< V
CC
V
CC
= Max.,
I
OUT
= 0 mA, Freq. = 20 MHz
All Inputs = V
IH
min.
Test Conditions
V
CC
= Min., I
OH
=
−2.0
mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
−0.5
–10
–10
Min.
2.4
0.4
V
CC
0.8
+10
+10
60
8
Max.
Unit
V
V
V
V
µA
µA
mA
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 4.5V
Max.
10
12
Unit
pF
pF
Notes:
1. T
A
is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second.
4. Tested initially and after any design or process changes that may affect these parameters.
2
FPGA/CPLD
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