a
KEY FEATURES
350 MHz High Performance Blackfin Processor Core
Two 16-Bit MACs, Two 40-Bit ALUs, One 40-Bit Shifter,
Four 8-Bit Video ALUs, and Two 40-Bit Accumulators
RISC-Like Register and Instruction Model for Ease of
Programming and Compiler Friendly Support
Advanced Debug, Trace, and Performance Monitoring
1.0 V–1.6 V Core V
DD
with Dynamic Power Management
3.3 V I/O
260-Ball PBGA Package
MEMORY
308K Bytes of On-Chip Memory:
16K Bytes of Instruction L1 SRAM/Cache
32K Bytes of Data L1 SRAM/Cache
4K Bytes of Scratch Pad L1 SRAM
256K Bytes of Full Speed, Low Latency L2 SRAM
Memory DMA Controller
Blackfin
®
Embedded Processor
ADSP-BF535
Memory Management Unit for Memory Protection
Glueless External Memory Controllers
Synchronous SDRAM Support
Asynchronous with SRAM, Flash, ROM Support
PERIPHERALS
32-Bit, 33 MHz, 3.3 V, PCI 2.2 Compliant Bus Interface
with Master and Slave Support
Integrated USB 1.1 Compliant Device Interface
Two UARTs, One with IrDA
®
Two SPI Compatible Ports
Two Full-Duplex Synchronous Serial Ports (SPORTs)
Four Timer/Counters, Three with PWM Support
Sixteen Bidirectional Programmable Flag I/O Pins
Watchdog Timer
Real-Time Clock
On-Chip PLL with 1 to 31 Frequency Multiplier
FUNCTIONAL BLOCK DIAGRAM
JTAG TEST AND
EMULATION
SO
MMU
L1
DATA
MEMORY
64
32
DMA
CONTROLLER
BOOT ROM
INTERRUPT
CONTROLLER/
TIMER
L1
INSTRUCTION
MEMORY
O
B
SYSTEM BUS
INTERFACE UNIT
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective
owners.
LE
TE
32
WATCHDOG TIMER
B
256K BYTES L2 SRAM
32
REAL-TIME CLOCK
UART PORT 0
IrDA
UART PORT 1
TIMER0, TIMER1,
TIMER2
PROGRAMMABLE
FLAGS
USB INTERFACE
SERIAL PORTS (2)
SPI PORTS (2)
32
PCI BUS INTERFACE
32
EXTERNAL PORT
FLASH SDRAM
CONTROL
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
.
ADSP-BF535
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2
Portable Low Power Architecture . . . . . . . . . . . . . . . 2
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
ADSP-BF535 Peripherals . . . . . . . . . . . . . . . . . . . . . 3
Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal (On-Chip) Memory . . . . . . . . . . . . . . . . . . 5
External (Off-Chip) Memory . . . . . . . . . . . . . . . . . 5
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 5
Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Event Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Core Event Controller (CEC) . . . . . . . . . . . . . . . . 6
System Interrupt Controller (SIC) . . . . . . . . . . . . . 6
Event Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
External Memory Control . . . . . . . . . . . . . . . . . . . . . 8
PC133 SDRAM Controller . . . . . . . . . . . . . . . . . . 8
Asynchronous Controller . . . . . . . . . . . . . . . . . . . . 8
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PCI Host Function . . . . . . . . . . . . . . . . . . . . . . . . . 8
PCI Target Function . . . . . . . . . . . . . . . . . . . . . . . 8
USB Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Ports (Sports) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . 10
UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Programmable Flags (PFX) . . . . . . . . . . . . . . . . . . . 11
Dynamic Power Management . . . . . . . . . . . . . . . . . 11
Full On Operating Mode
– Maximum Performance . . . . . . . . . . . . . . . . . 11
Active Operating Mode
– Moderate Power Savings . . . . . . . . . . . . . . . . 11
Sleep Operating Mode
– High Power Savings . . . . . . . . . . . . . . . . . . . . 11
Deep Sleep Operating Mode
– Maximum Power Savings . . . . . . . . . . . . . . . . 12
Mode Transitions . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Peripheral Power Control . . . . . . . . . . . . . . . . . . . 13
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instruction Set Description . . . . . . . . . . . . . . . . . . . 14
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 15
EZ-KITLite™ forADSP-BF535 Blackfin Processor 16
Designing an Emulator Compatible
Processor Board (Target) . . . . . . . . . . . . . . . . . 16
Additional Information . . . . . . . . . . . . . . . . . . . . . . 16
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 17
Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 22
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 22
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 23
Clock and Reset Timing . . . . . . . . . . . . . . . . . . . . 24
O
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SO
–2–
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GENERAL DESCRIPTION
Portable Low Power Architecture
System Integration
Programmable Flags Cycle Timing . . . . . . . . . . .
Timer PWM_OUT Cycle Timing . . . . . . . . . . . .
Asynchronous Memory Write Cycle Timing . . . .
Asynchronous Memory Read Cycle Timing . . . . .
SDRAM Interface Timing . . . . . . . . . . . . . . . . . .
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI) Port
—Master Timing . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI) Port
—Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing .
JTAG Test and Emulation Port Timing . . . . . . . .
Output Drive Currents . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . .
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Enable Time . . . . . . . . . . . . . . . . . . . .
Output Disable Time . . . . . . . . . . . . . . . . . . . .
Example System Hold Time Calculation . . . . .
Environmental Conditions . . . . . . . . . . . . . . . . . .
260-Ball PBGA Pinout . . . . . . . . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . .
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . .
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The ADSP-BF535 processor is a member of the Blackfin
processor family of products, incorporating the Micro Signal
Architecture (MSA), jointly developed by Analog Devices, Inc.
and Intel Corporation. The architecture combines a dual MAC
state-of-the-art signal processing engine, the advantages of a
clean, orthogonal RISC-like microprocessor instruction set, and
Single-Instruction, Multiple Data (SIMD) multimedia capabili-
ties into a single instruction set architecture.
By integrating a rich set of industry leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like programma-
bility, multimedia support, and leading edge signal processing in
one integrated package.
Blackfin processors provide world class power management and
performance. Blackfin processors are designed in a low power
and low voltage design methodology and feature dynamic power
management, the ability to independently vary both the voltage
and frequency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a
substantial reduction in power consumption, by comparison to
just varying the frequency of operation. This translates into
longer battery life for portable appliances.
The ADSP-BF535 Blackfin processor is a highly integrated
system-on-a-chip solution for the next generation of digital com-
munication and portable Internet appliances. By combining
industry-standard interfaces with a high performance signal
processing core, users can develop cost-effective solutions
quickly without the need for costly external components. The
ADSP-BF535 Blackfin processor system peripherals include
UARTs, SPIs, SPORTs, general-purpose Timers, a Real-Time
REV. A
ADSP-BF535
Clock, Programmable Flags, Watchdog Timer, and USB and
PCI buses for glueless peripheral expansion.
ADSP-BF535 Peripherals
O
B
P5
P4
P3
P2
P1
P0
I1
I0
R7
R6
R5
R4
R3
R2
R1
R0
8
SO
SP
FP
I3
I2
L3
L2
B3
B2
B1
B0
M3
M2
M1
M0
L1
L0
16
8
BA RR EL
SHIF T ER
40
A0
DA T A AR ITH MET IC UN IT
The on-chip peripherals can be easily augmented in many system
designs with little or no glue logic due to the inclusion of several
interfaces providing expansion on industry-standard buses.
These include a 32-bit, 33 MHz, V2.2 compliant PCI bus, SPI
serial expansion ports, and a device type USB port. These enable
the connection of a large variety of peripheral devices to tailor the
system design to specific applications with a minimum of design
complexity.
ADD RESS A RIT HMET IC U NIT
REV. A
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TE
DA G0
D A G1
SEQU ENCE R
AL IGN
DEC ODE
L OOP BUF F ER
16
8
8
CON TR OL
U NIT
40
A1
The ADSP-BF535 Blackfin processor contains a rich set of
peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance. See Functional Block
Diagram
on Page 1.
The base peripherals include general-
purpose functions such as UARTs, timers with PWM (Pulse
Width Modulation) and pulse measurement capability, general-
purpose flag I/O pins, a real-time clock, and a watchdog timer.
This set of functions satisfies a wide variety of typical system
support needs and is augmented by the system expansion capa-
bilities of the part. In addition to these general-purpose
peripherals, the ADSP-BF535 Blackfin processor contains high
speed serial ports for interfaces to a variety of audio and modem
CODEC functions. It also contains an event handler for flexible
management of interrupts from the on-chip peripherals and
external sources. And it contains power management control
functions to tailor the performance and power characteristics of
the processor and system to many application scenarios.
All of the peripherals, except for programmable flags, real-time
clock, and timers, are supported by a flexible DMA structure with
individual DMA channels integrated into the peripherals. There
is also a separate memory DMA channel dedicated to data
transfers between the various memory spaces including external
SDRAM and asynchronous memory, internal Level 1 and Level
2 SRAM, and PCI memory spaces. Multiple on-chip 32-bit
buses, running at up to 133 MHz, provide adequate bandwidth
to keep the processor core running along with activity on all of
the on-chip and external peripherals.
Processor Core
As shown in
Figure 1,
the Blackfin processor core contains two
multiplier/accumulators (MACs), two 40-bit ALUs, four video
ALUs, and a single shifter. The computational units process
8-bit, 16-bit, or 32-bit data from the register file.
Each MAC performs a 16-bit by 16-bit multiply in every cycle,
with an accumulation to a 40-bit result, providing 8 bits of
extended precision.
The ALUs perform a standard set of arithmetic and logical oper-
ations. With two ALUs capable of operating on 16- or 32-bit data,
the flexibility of the computation units covers the signal process-
ing requirements of a varied set of application needs. Each of the
two 32-bit input registers can be regarded as two 16-bit halves,
so each ALU can accomplish very flexible single 16-bit arithmetic
operations. By viewing the registers as pairs of 16-bit operands,
dual 16-bit or single 32-bit operations can be accomplished in a
single cycle. Quad 16-bit operations can be accomplished simply,
by taking advantage of the second ALU. This accelerates the per
cycle throughput.
Figure 1. Processor Core
–3–
ADSP-BF535
The powerful 40-bit shifter has extensive capabilities for perform-
ing shifting, rotating, normalization, extraction, and for
depositing data.
The data for the computational units is found in a multiported
register file of sixteen 16-bit entries or eight 32-bit entries.
A powerful program sequencer controls the flow of instruction
execution, including instruction alignment and decoding. The
sequencer supports conditional jumps and subroutine calls, as
well as zero-overhead looping. A loop buffer stores instructions
locally, eliminating instruction memory accesses for tightly
looped code.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from memory. The DAGs
share a register file containing four sets of 32-bit Index, Modify,
Length, and Base registers. Eight additional 32-bit registers
provide pointers for general indexing of variables and stack
locations.
address spaces, and I/O control registers, occupy separate
sections of this common address space. The memory portions of
this address space are arranged in a hierarchical structure to
provide a good cost/performance balance with very fast, low
latency memory as cache or SRAM very close to the processor;
and larger, lower cost, and lower performance memory systems
farther away from the processor. See
Figure 2.
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
RESERVED
INTERNAL MEMORY MAP
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. Level 2 (L2) memories are other
memories, on-chip or off-chip, that may take multiple processor
cycles to access. At the L1 level, the instruction memory holds
instructions only. The two data memories hold data, and a
dedicated scratch pad data memory stores stack and local variable
information. At the L2 level, there is a single unified memory
space, holding both instructions and data.
SO
–4–
O
B
The architecture provides three modes of operation: user mode,
supervisor mode, and Emulation mode. User mode has restricted
access to certain system resources, thus providing a protected
software environment, while supervisor mode has unrestricted
access to the system and core resources.
The Blackfin processor instruction set has been optimized so that
16-bit op-codes represent the most frequently used instructions,
resulting in excellent compiled code density. Complex DSP
instructions are encoded into 32-bit op-codes, representing fully
featured multifunction instructions. Blackfin processors support
a limited multiple issue capability, where a 32-bit instruction can
be issued in parallel with two 16-bit instructions, allowing the
programmer to use many of the core resources in a single
instruction cycle.
The Blackfin processor assembly language uses an algebraic
syntax for ease of coding and readability. The architecture has
been optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
Memory Architecture
PCI MEMORY SPACE (128M BYTE)
RESERVED
ASYNC MEMORY BANK 3 (64M BYTE)
0xE000 0000
0x2FFF FFFF
0x2C00 0000
ASYNC MEMORY BANK 2 (64M BYTE)
0x2800 0000
ASYNC MEMORY BANK 1 (64M BYTE)
0x2400 0000
ASYNC MEMORY BANK 0 (64M BYTE)
0x2000 0000
0x1800 0000
0x1000 0000
0x0800 0000
0x0000 0000
SDRAM MEMORY BANK 3
(16M BYTE - 128M BYTE)
1
SDRAM MEMORY BANK 2
(16M BYTE - 128M BYTE)
1
SDRAM MEMORY BANK 1
(16M BYTE - 128M BYTE)
1
SDRAM MEMORY BANK 0
(16M BYTE - 128M BYTE)
1
1
THE ADDRESSES SHOWN FOR THE SDRAM BANKS REFLECT A FULLY
POPULATED SDRAM ARRAY WITH 512M BYTES OF MEMORY. IF ANY BANK
CONTAINS LESS THAN 128M BYTES OF MEMORY, THAT BANK WOULD
EXTEND ONLY TO THE LENGTH OF THE REAL MEMORY SYSTEMS, AND THE
END ADDRESS WOULD BECOME THE START ADDRESS OF THE NEXT BANK.
THIS WOULD CONTINUE FOR ALL FOUR BANKS, WITH ANY REMAINING SPACE
BETWEEN THE END OF MEMORY BANK 3 AND THE BEGINNING OF ASYNC
MEMORY BANK 0, AT ADDRESS 0x2000 0000, TREATED AS RESERVED
ADDRESS SPACE.
The ADSP-BF535 Blackfin processor views memory as a single
unified 4 Gbyte address space, using 32-bit addresses. All
resources, including internal memory, external memory, PCI
Figure 2. Internal/External Memory Map
REV. A
EXTERNAL MEMORY MAP
In addition, the L1 instruction memory and L1 data memories
may be configured as either Static RAMs (SRAMs) or caches.
The Memory Management Unit (MMU) provides memory pro-
tection for individual tasks that may be operating on the core and
may protect system registers from unintended access.
LE
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0xFFB0 0000
0xFFA0 4000
0xFFA0 0000
0xFF90 4000
0xFF90 0000
0xFF80 4000
0xFF80 0000
INSTRUCTION SRAM (16K BYTE)
RESERVED
DATA BANK B SRAM (16K BYTE)
RESERVED
DATA BANK A SRAM (16K BYTE)
RESERVED
0xF003 FFFF
0xF000 0000
L2 SRAM MEMORY (256K BYTE)
RESERVED
0xEF00 0000
PCI CONFIG SPACE PORT (4 BYTE)
0xEEFF FFFC
0xEEFF FF00
RESERVED
PCI IO SPACE (64K BYTE)
RESERVED
0xEEFE FFFF
0xEEFE 0000
0xE7FF FFFF
PCI CONFIG REGISTERS (64K BYTE)
ADSP-BF535
The L1 memory system is the primary highest performance
memory available to the Blackfin processor core. The L2 memory
provides additional capacity with slightly lower performance.
Lastly, the off-chip memory system, accessed through the
External Bus Interface Unit (EBIU), provides expansion with
SDRAM, flash memory, and SRAM, optionally accessing more
than 768M bytes of external physical memory.
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal L1/L2 memories and the external
memory spaces (including PCI memory space).
Internal (On-Chip) Memory
64 Mbyte segment regardless of the size of the devices used so
that these banks will only be contiguous if fully populated with
64M bytes of memory.
PCI
The PCI bus defines three separate address spaces, which are
accessed through windows in the ADSP-BF535 Blackfin
processor memory space. These spaces are PCI memory, PCI
I/O, and PCI configuration.
In addition, the PCI interface can either be used as a bridge from
the processor core as the controlling CPU in the system, or as a
host port where another CPU in the system is the host and the
ADSP-BF535 is functioning as an intelligent I/O device on the
PCI bus.
When the ADSP-BF535 Blackfin processor acts as the system
controller, it views the PCI address spaces through its mapped
windows and can initialize all devices in the system and maintain
a map of the topology of the environment.
The PCI memory region is a 4 Gbyte space that appears on the
PCI bus and can be used to map memory I/O devices on the bus.
The ADSP-BF535 Blackfin processor uses a 128 Mbyte window
in memory space to see a portion of the PCI memory space. A
base address register is provided to position this window
anywhere in the 4 Gbyte PCI memory space while its position
with respect to the processor addresses remains fixed.
The PCI I/O region is also a 4 Gbyte space. However, most
systems and I/O devices only use a 64 Kbyte subset of this space
for I/O mapped addresses. The ADSP-BF535 Blackfin processor
implements a 64K byte window into this space along with a base
address register which can be used to position it anywhere in the
PCI I/O address space, while the window remains at the same
address in the processor's address space.
PCI configuration space is a limited address space, which is used
for system enumeration and initialization. This address space is
a very low performance communication mode between the
processor and PCI devices. The ADSP-BF535 Blackfin
processor provides a one-value window to access a single data
value at any address in PCI configuration space. This window is
fixed and receives the address of the value, and the value if the
operation is a write. Otherwise, the device returns the value into
the same address on a read operation.
I/O Memory Space
The first is the L1 instruction memory consisting of 16K bytes
of 4-Way set-associative cache memory. In addition, the memory
may be configured as an SRAM. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of two banks of 16K bytes each. Each L1 data memory
bank can be configured as one Way of a 2-Way set-associative
cache or as an SRAM, and is accessed at full speed by the core.
The third memory block is a 4K byte scratch pad RAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM (it cannot be configured as cache memory and is
not accessible via DMA).
The fourth on-chip memory system is the L2 SRAM memory
array which provides 256K bytes of high speed SRAM at the full
bandwidth of the core, and slightly longer latency than the L1
memory banks. The L2 memory is a unified instruction and data
memory and can hold any mixture of code and data required by
the system design.
The Blackfin processor core has a dedicated low latency 64-bit
wide datapath port into the L2 SRAM memory.
External (Off-Chip) Memory
O
B
REV. A
External memory is accessed via the External Bus Interface Unit
(EBIU). This interface provides a glueless connection to up to
four banks of synchronous DRAM (SDRAM) as well as up to
four banks of asynchronous memory devices including flash,
EPROM, ROM, SRAM, and memory-mapped I/O devices.
The PC133 compliant SDRAM controller can be programmed
to interface to up to four banks of SDRAM, with each bank
containing between 16M bytes and 128M bytes providing access
to up to 512M bytes of SDRAM. Each bank is independently
programmable and is contiguous with adjacent banks regardless
of the sizes of the different banks or their placement. This allows
flexible configuration and upgradability of system memory while
allowing the core to view all SDRAM as a single, contiguous,
physical address space.
The asynchronous memory controller can also be programmed
to control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
SO
–5–
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The ADSP-BF535 Blackfin processor has four blocks of on-chip
memory providing high bandwidth access to the core.
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4 Gbyte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for setup
and control of the on-chip peripherals outside of the core. The
core MMRs are accessible only by the core and only in supervisor
mode and appear as reserved space by on-chip peripherals, as
well as external devices accessing resources through the PCI bus.
The system MMRs are accessible by the core in supervisor mode
and can be mapped as either visible or reserved to other devices,
depending on the system protection model desired.
Embedded System
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