AT25640AY1-10YI-2.7 datasheet, PDF

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AT25640AY1-10YI-2.7: Description8K X 8 SPI BUS SERIAL EEPROM, PDSO8; Categorystorage storage; File Size376KB，20 Pages; ManufacturerAtmel (Microchip)

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AT25640AY1-10YI-2.7 Overview

8K X 8 SPI BUS SERIAL EEPROM, PDSO8

AT25640AY1-10YI-2.7 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	SOIC
package instruction	VSON, SOLCC8,.2,25
Contacts	8
Reach Compliance Code	compli
ECCN code	EAR99
Maximum clock frequency (fCLK)	10 MHz
Data retention time - minimum	100
Durability	1000000 Write/Erase Cycles
JESD-30 code	R-XDSO-N8
JESD-609 code	e0
length	4.9 mm
memory density	65536 bi
Memory IC Type	EEPROM
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of terminals	8
word count	8192 words
character code	8000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8KX8
Package body material	UNSPECIFIED
encapsulated code	VSON
Encapsulate equivalent code	SOLCC8,.2,25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	240
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	0.9 mm
Serial bus type	SPI
Maximum standby current	0.000002 A
Maximum slew rate	0.01 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3 mm
Maximum write cycle time (tWC)	5 ms
write protect	HARDWARE/SOFTWARE

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Features

•

Serial Peripheral Interface (SPI) Compatible

•

Supports SPI Modes 0 (0,0) and 3 (1,1)

•

– Data Sheet Describes Mode 0 Operation

Medium-voltage and Standard-voltage Operation

– 2.7 (V

= 2.7V to 5.5V)

Extended Temperature Range –40°C to 125°C

5.0 MHz Clock Rate

32-byte Page Mode

Block Write Protection

– Protect 1/4, 1/2, or Entire Array

Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software

Data Protection

Self-timed Write Cycle (2 ms [5V] typical)

High Reliability

– Endurance: One Million Write Cycles

– Data Retention: 100 Years

8-lead PDIP, 8-lead JEDEC SOIC Packages and 8-lead TSSOP Packages

Description

The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial

electrically-erasable programmable read-only memory (EEPROM) organized as

1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many

automotive applications where low-power and low-voltage operation are essential.

The AT25080A/160A/320A/640A is available in space-saving 8-lead PDIP, 8-lead

JEDEC SOIC and 8-lead TSSOP packages.

The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS) and

accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data

Output (SO), and Serial Clock (SCK). All programming cycles are completely self-

timed, and no separate erase cycle is required before write.

Block write protection is enabled by programming the status register with one of four

blocks of write protection. Separate program enable and program disable instructions

are provided for additional data protection. Hardware data protection is provided via

the WP pin to protect against inadvertent write attempts to the status register. The

HOLD pin may be used to suspend any serial communication without resetting the

serial sequence.

Table 1.

Pin Configurations

Pin Name

SCK

GND

VCC

HOLD

Function

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

Power Supply

Write Protect

Suspends Serial Input

No Connect

Don’t Connect

GND

SPI Serial

Extended

Temperature

EEPROMs

8K (1024 x 8)

16K (2048 x 8)

32K (4096 x 8)

64K (8192 x 8)

AT25080A

AT25160A

AT25320A

AT25640A

8-lead

PDIP

VCC

HOLD

SCK

8-lead SOIC

GND

VCC

HOLD

SCK

8-lead

TSSOP

VCC

HOLD

SCK

5082B–SEEPR–1/05

AT25080A/160A/320A/640A

Serial Interface

Description

MASTER:

The device that generates the serial clock.

S L AV E :

B e c a u s e t h e s e r i a l c l o c k p i n ( S C K ) i s a l w a y s a n i n p u t , t h e

AT25080A/160A/320A/640A always operates as a slave.

TRANSMITTER/RECEIVER:

The AT25080A/160A/320A/640A has separate pins des-

ignated for data transmission (SO) and reception (SI).

MSB:

The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE:

After the device is selected with CS going low, the first byte will be

received. This byte contains the op-code that defines the operations to be performed.

INVALID OP-CODE:

If an invalid op-code is received, no data will be shifted into the

AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high imped-

ance state until the falling edge of CS is detected again. This will reinitialize the serial

communication.

CHIP SELECT:

The AT25080A/160A/320A/640A is selected when the CS pin is low.

When the device is not selected, data will not be accepted via the SI pin, and the serial

output pin (SO) will remain in a high impedance state.

HOLD:

The HOLD pin is used in conjunction with the CS pin to select the

AT25080A/160A/320A/640A. When the device is selected and a serial sequence is

underway, HOLD can be used to pause the serial communication with the master device

without resetting the serial sequence. To pause, the HOLD pin must be brought low

while the SCK pin is low. To resume serial communication, the HOLD pin is brought high

while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be

ignored while the SO pin is in the high impedance state.

WRITE PROTECT:

The write protect pin (WP) will allow normal read/write operations

when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera-

tions to the status register are inhibited. WP going low while CS is still low will interrupt a

write to the status register. If the internal write cycle has already been initiated, WP

going low will have no effect on any write operation to the status register. The WP pin

function is blocked when the WPEN bit in the status register is "0". This will allow the

user to install the AT25080A/160A/320A/640A in a system with the WP pin tied to

ground and still be able to write to the status register. All WP pin functions are enabled

when the WPEN bit is set to “1”.

5082B–SEEPR–1/05

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