a
FEATURES
Low Cost
Low Power
2.0 W @ 2.5 V (Outputs Enabled)
<100 mW @ 2.5 V (Outputs Disabled)
34 34, Fully Differential, Nonblocking Array
3.2 Gbps per Port NRZ Data Rate
Wide Power Supply Range: 2.5 V to 3.3 V
LVTTL or LVCMOS Level Control Inputs:
@ 2.5 V to 3.3 V
Low Jitter: 45 ps
Drives a Backplane Directly
Programmable Output Swing
100 mV to 1.6 V Differential
50 On-Chip I/O Termination
User Controlled Voltage at the Load
Minimizes Power Dissipation
Dual Rank Latches
Available in 256-Ball Grid Array
34 34, 3.2 Gbps
Asynchronous Digital Crosspoint Switch
AD8152
*
FUNCTIONAL BLOCK DIAGRAM
VCC
34
INP
VTTI
34
INN
34
OUTP
34 34
DIFFERENTIAL
SWITCH MATRIX
OUTPUT
LEVEL
DACs
VTTO
34
OUTN
D[5:0]
MATRIX
CONNECTION
LATCHES
CONNECTION
DECODE
OUTPUT
LEVEL
LATCHES
RESET
CS
A[6:0]
RE
WE
UPDATE
VEE
CONTROL
LOGIC
AD8152
APPLICATIONS
Fiber Optic Network Switching
High Speed Serial Backplane Routing to OC-48 with FEC
Gigabit Ethernet
Digital Video (HDTV)
Data Storage Networks
GENERAL DESCRIPTION
AD8152 is a member of the Xstream line of products and is a
breakthrough in digital switching, offering a large switch array
(34
×
34) on very little power, typically 2.0 W. Additionally, it
operates at data rates up to 3.2 Gbps per port, making it suitable
for Sonet/SDH OC-48 with Forward Error Correction (FEC).
The AD8152’s useful supply voltage range allows the user to
operate at LVPECL/CML data levels down to 2.5 V. The control
interface is LVTTL or LVCMOS compatible on 2.5 V to 3.3 V.
The AD8152’s fully differential signal path reduces jitter and
crosstalk while allowing the use of smaller single-ended voltage
swings. It is offered in a 256-ball SBGA package that operates
over the industrial temperature range of 0°C to 85°C.
100mV/DIV
80ps/DIV
Figure 1. Eye Pattern, 3.2 Gbps, PRBS 23
*Patent
Pending
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD8152
ELECTRICAL CHARACTERISTICS
Parameter
DYNAMIC PERFORMANCE
Max Data Rate/Channel (NRZ)
Channel Jitter
RMS Channel Jitter
Propagation Delay
Propagation Delay Match
Output Rise/Fall Time
INPUT CHARACTERISTICS
Input Voltage Swing
Input Voltage Range
Input Bias Current
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Output Current
Output Capacitance
TERMINATION CHARACTERISTICS
Resistance
Temperature Coefficient
POWER SUPPLY
Operating Range
VCC
Quiescent Current
VCC
VEE
(@ 25 C, VCC = 2.5 V to 3.3 V, VEE = 0 V, R
L
= 50
unless otherwise noted.)
Min
3.2
, Differential Output Swing = 800 mV p-p,
Condition
Typ
Max
Unit
Gbps
ps p-p
ps
ps
ps
ps
mV p-p
V
mA
pF
mV p-p
V
mA
pF
W
W/∞C
Data Rate
£
3.2 Gbps; PRBS 2
23
– 1
Input to Output
20% to 80%
Single-Ended (See TPC 14)
Common-Mode (See TPC 15)
45
<10
660
±
50
100
50
VEE + 0.8
2
2
800
±
120
1000
VCC + 0.2
Differential (See TPC 18)
100
800
VCC – 1.2
2
2
43
50
0.05
1600
VCC + 0.2
32
57
VEE = 0 V
All Outputs Disabled
All Outputs Enabled
All Outputs Disabled
All Outputs Enabled
T
MIN
to T
MAX,
All Outputs Enabled
VCC = 3.3 V
VCC = 3.3 V
VCC = 2.5 V
VCC = 2.5 V
VCC = 3.3 V, IOH = –2 mA
VCC = 3.3 V, IOL = +2 mA
VCC = 2.5 V, IOH = –100 uA
VCC = 2.5 V, IOL = +100 uA
2.25
32
190
32
770
800
2
3.63
45
45
V
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
∞C
∞C/W
∞C/W
∞C/W
LOGIC INPUT CHARACTERISTICS
Input High (VIH)
Input Low (VIL)
Input High (VIH)
Input Low (VIL)
LOGIC OUTPUT CHARACTERISTICS
Output High (VOH)
Output Low (VOL)
Output High (VOH)
Output Low (VOL)
THERMAL CHARACTERISTICS
Operating Temperature Range
JA
0.8
1.7
0.7
2.4
0.4
2.1
0.2
0
85
15
12
11
Still Air
200 lfpm
400 lfpm
Specifications subject to change without notice.
–2–
REV. A
AD8152
ABSOLUTE MAXIMUM RATINGS
1
MAXIMUM POWER DISSIPATION – W
16
Tj = 150 C
14
12
400 lfpm
10
200 lfpm
8
STILL AIR
6
4
2
0
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 V
VTTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V
VTTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V
Internal Power Dissipation
2
AD8152 256-Ball SBGA (BP) . . . . . . . . . . . . . . . . . . 8.33 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 1.7 V
Logic Input Voltage . . . . . . VEE – 0.3 V < V
IN
< VCC + 0.6 V
Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for the device in free air (T
A
= 25°C):
JA
= 15°C/W @ still air.
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE – C
80
90
Figure 2. Maximum Power Dissipation vs. Temperature
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8152 is
limited by the associated rise in junction temperature. The maxi-
mum safe junction temperature for plastic encapsulated devices
is determined by the glass transition temperature of the plastic,
approximately 150°C. Temporarily exceeding this limit may cause
a shift in parametric performance due to a change in the stresses
exerted on the die by the package. Exceeding a junction tem-
perature of 175°C for an extended period can result in device
failure. To ensure proper operation, it is necessary to observe the
maximum power derating curves shown in Figure 2.
ORDERING GUIDE
Model
AD8152JBP
AD8152-EVAL
Temperature Range
0°C to 85°C
Package Description
256-Ball SBGA (27 mm
×
27 mm)
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8152 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. A
–3–
AD8152
BALL GRID ARRAY
20
A
VEE
19
VEE
18
VEE
17
VEE
16
VCC
15
VTTO
14
O14P
13
VTTO
12
O11P
11
VCC
10
O08P
9
VTTO
8
O05P
7
VTTO
6
O02P
5
VTTO
4
VCC
3
VEE
2
VEE
1
VEE
A
B
VEE
VEE
VEE
VEE
VCC
VTTO
O14N
VTTO
O11N
VCC
O08N
VTTO
O05N
VTTO
O02N
VTTO
VCC
VEE
VEE
VEE
B
C
VEE
VEE
D4
D5
O16N
O15P
O13N
O12P
O10N
O09P
O07N
O06P
O04N
O03P
O01N
O00P
A6
A5
VEE
VEE
C
D
D0
D1
D2
D3
O16P
O15N
O13P
O12N
O10P
O09N
O07P
O06N
O04P
O03N
O01P
O00N
A4
A3
A2
A1
D
E
CS
RESET
N/C
N/C
N/C
N/C
UPDATE
A0
E
F
VCC
RE
I17P
I17N
I00N
I00P
WE
VCC
F
G
I19P
I19N
I18N
I18P
I01P
I01N
I02N
I02P
G
H
VTTI
VTTI
I20P
I20N
I03N
I03P
VTTI
VTTI
H
J
I22P
I22N
I21N
I21P
I04P
I04N
I05N
I05P
J
K
VTTI
VTTI
I23P
I23N
I06N
I06P
VTTI
VTTI
K
L
I25P
I25N
I24N
I24P
I07P
I07N
I08N
I08P
L
M
VCC
VCC
I26P
I26N
I09N
I09P
VCC
VCC
M
N
I28P
I28N
I27N
I27P
I10P
I10N
I11N
I11P
N
P
VTTI
VTTI
I29P
I29N
I12N
I12P
VTTI
VTTI
P
R
I31P
I31N
I30N
I30P
I13P
I13N
I14N
I14P
R
T
VTTI
VTTI
I32P
I32N
I15N
I15P
VTTI
VTTI
T
U
VCC
VCC
I33N
I33P
O33P
O32N
O30P
O29N
O27P
O26N
O24P
O23N
O21P
O20N
O18P
O17N
I16P
I16N
VCC
VCC
U
V
VEE
VEE
VEE
VEE
O33N
O32P
O30N
O29P
O27N
O26P
O24N
O23P
O21N
O20P
O18N
O17P
VEE
VEE
VEE
VEE
V
W
VEE
VEE
VEE
VEE
VCC
VTTO
O31N
VTTO
O28N
VCC
O25N
VTTO
O22N
VTTO
O19N
VTTO
VCC
VEE
VEE
VEE
W
Y
VEE
VEE
VEE
VEE
VCC
VTTO
O31P
VTTO
O28P
VCC
O25P
VTTO
O22P
VTTO
O19P
VTTO
VCC
VEE
VEE
VEE
Y
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Ball Diagram, View from the Bottom
–4–
REV. A
AD8152
BALL GRID DESCRIPTIONS
Ball
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
Mnemonic
VEE
VEE
VEE
VCC
VTTO
OUT02P
VTTO
OUT05P
VTTO
OUT08P
VCC
OUT11P
VTTO
OUT14P
VTTO
VCC
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VCC
VTTO
OUT02N
VTTO
OUT05N
VTTO
OUT08N
VCC
OUT11N
VTTO
OUT14N
VTTO
VCC
VEE
VEE
VEE
VEE
VEE
VEE
A5
A6
OUT00P
OUT01N
OUT03P
OUT04N
OUT06P
OUT07N
OUT09P
Type
Power
Power
Power
Power
Power
I/O
Power
I/O
Power
I/O
Power
I/O
Power
I/O
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
I/O
Power
I/O
Power
I/O
Power
I/O
Power
I/O
Power
Power
Power
Power
Power
Power
Power
Power
Control
Control
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Negative Supply
Negative Supply
Negative Supply
Positive Supply
Output Termination Supply
High Speed Output
Output Termination Supply
High Speed Output
Output Termination Supply
High Speed Output
Positive Supply
High Speed Output
Output Termination Supply
High Speed Output
Output Termination Supply
Positive Supply
Negative Supply
Negative Supply
Negative Supply
Negative Supply
Negative Supply
Negative Supply
Negative Supply
Positive Supply
Output Termination Supply
High Speed Output Complement
Output Termination Supply
High Speed Output Complement
Output Termination Supply
High Speed Output Complement
Positive Supply
High Speed Output Complement
Output Termination Supply
High Speed Output Complement
Output Termination Supply
Positive Supply
Negative Supply
Negative Supply
Negative Supply
Negative Supply
Negative Supply
Negative Supply
Output Address Pin (MSB)
Output Address Pin (Bank Des.)
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
–5–
Ball
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E1
E2
E3
E4
E17
E18
E19
E20
F1
F2
F3
F4
F17
F18
F19
F20
G1
G2
G3
G4
G17
G18
Mnemonic
OUT10N
OUT12P
OUT13N
OUT15P
OUT16N
D5
D4
VEE
VEE
A1
A2
A3
A4
OUT00N
OUT01P
OUT03N
OUT04P
OUT06N
OUT07P
OUT09N
OUT10P
OUT12N
OUT13P
OUT15N
OUT16P
D3
D2
D1
D0
A0
UPDATE
N/C Reserved
N/C Reserved
N/C Reserved
N/C Reserved
RESET
CS
VCC
WE
IN00P
IN00N
IN17N
IN17P
RE
VCC
IN02P
IN02N
IN01N
IN01P
IN18P
IN18N
Type
I/O
I/O
I/O
I/O
I/O
Control
Control
Power
Power
Control
Control
Control
Control
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Control
Control
Control
Control
Control
Control
Control
Control
Power
Control
I/O
I/O
I/O
I/O
Control
Power
I/O
I/O
I/O
I/O
I/O
I/O
Description
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
Input Address Pin (MSB)
Input Address Pin
Negative Supply
Negative Supply
Output Address Pin
Output Address Pin
Output Address Pin
Output Address Pin
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
High Speed Output Complement
High Speed Output
Input Address Pin
Input Address Pin
Input Address Pin
Input Address Pin (LSB)
Output Address Pin (LSB)
Second Rank Write Enable
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Reset/Disable Outputs
Chip Select Enable
Positive Supply
First Rank Write Enable
High Speed Input
High Speed Input Complement
High Speed Input Complement
High Speed Input
Readback Enable
Positive Supply
High Speed Input
High Speed Input Complement
High Speed Input Complement
High Speed Input
High Speed Input
High Speed Input Complement
REV. A
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