W83195BR-25/W83195BG-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
Table of Contents-
1.
2.
3.
4.
GENERAL DESCRIPTION ......................................................................................................... 1
PRODUCT FEATURES .............................................................................................................. 1
PIN CONFIGURATION ............................................................................................................... 2
PIN DESCRIPTION..................................................................................................................... 3
4.1
4.2
4.3
4.4
4.5
5.
6.
Crystal I/O.................................................................................................................................3
CPU, SDRAM, PCI, IOAPIC Clock Outputs............................................................................3
I2C Control Interface ................................................................................................................4
Fixed Frequency Outputs.........................................................................................................4
Power Pins................................................................................................................................5
FREQUENCY SELECTION BY HARDWARE ............................................................................ 6
SERIAL CONTROL REGISTERS............................................................................................... 7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
Register 0: CPU Frequency Select Register...........................................................................9
Register 1: CPU Clock Register (1 = Active, 0 = Inactive)......................................................9
Register 2: SDRAM Clock Register (1 = Active, 0 = Inactive) ................................................9
Register 3: PCI Clock Register (1 = Active, 0 = Inactive) .....................................................10
Register 4: Additional Register (1 = Active, 0 = Inactive)......................................................10
Register 5: SDRAM Clock Register (1 = Active, 0 = Inactive) ..............................................10
Register 6 Watchdog Timer Register ....................................................................................11
Register 7: M/N Program Register ........................................................................................11
Register 8: M/N Program Register ........................................................................................11
Register 9: Spread Spectrum Programming Register ..........................................................12
Register 10: Divisor and Step-less Enable Register .............................................................12
Register 11: Winbond Chip ID Register (Read Only).........................................................13
Register 12: Winbond Chip ID Register (Read Only).........................................................13
Absolute Maximum Ratings ...................................................................................................14
Electronical Characteristics---Input/Output............................................................................14
Electronical Characteristics of CPU Clock ............................................................................15
Electronical Characteristics of 3V66 Clock............................................................................15
Electronical Characteristics of SDRAM Clock.......................................................................16
Electronical Characteristics of PCI Clock ..............................................................................16
Electronical Characteristics of 48MHz, REF Clock ...............................................................17
7.
SPECIFICATIONS .................................................................................................................... 14
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8.
ORDERING INFORMATION..................................................................................................... 18
Publication Release Date: October 5, 2007
Revision 2.1
- II -
W83195BR-25/W83195BG-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
1. GENERAL DESCRIPTION
The W83195BR-25 is a Clock Synthesizer for Intel 815 Solano chipset. W83195BR-25 provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally
selectable with smooth transitions.
The W83195BR-25 provides I
2
C serial bus interface to program the registers to enable or disable each
clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI.
The W83195BR-25 provides step less frequency programming by controlling the VCO freq. and the
clock output divisor ratio. Also skew of CPU, SDRAM and 3V66 clock outputs are programmable. A
watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.
The W83195BR-25 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF
loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2. PRODUCT FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
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2 CPU clocks (2.5V)
3 3V-66 clocks (3.3V)
12 SDRAM clocks for 3 DIMMs(3.3V)
8 PCI synchronous clocks.
Optional single or mixed supply:
(VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V)
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
Smooth frequency switch with selections from 66.8 to 200MHz
I
2
C 2-Wire serial interface and I
2
C read back
0.25% center and 0.5% center type spread spectrum
Programmable registers to enable/stop each output and select modes
(Mode as Tri-state or Normal)
48 MHz for USB
24 MHz for super I/O
Packaged in 56-pin SSOP
-1-
Publication Release Date: October 5, 2007
Revision 2.1
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