PIC18F2458/2553/4458/4553
PIC18F2458/2553/4458/4553 Rev. B7 Silicon Errata
The PIC18F2458/2553/4458/4553 Rev. B7 parts you
have received conform functionally to the Device Data
Sheet (DS39887B), except for the anomalies
described below. Any Data Sheet Clarification issues
related to the PIC18F2458/2553/4458/4553 will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.
Note:
The
“PIC18F2458/2553/4458/4553 Data
Sheet”
is
supplemented
by
the
“PIC18F2455/2550/4455/4550 Data Sheet”
(DS39632). PIC18F2458/2553/4458/4553
features and specifications that are
shared with the PIC18F2455/2550/4455/
4550 devices are documented in
the
“PIC18F2455/2550/4455/4550 Data
Sheet”.
1. Module: MSSP
In SPI Slave mode with slave select enabled
(SSPM<3:0> =
0100),
the minimum time between
the falling edge of the SS pin and first SCK edge
is greater than specified in parameter 70
in Table 28-17 and Table 28-18 of the
“PIC18F2455/2550/4455/4550
Data
Sheet”
(DS39632). The updated specification is shown in
bold in Table 1.
The minimum time between SS pin low and an
SSPBUF write is also 3 T
CY
. If the falling edge of
the SS pin occurs greater than 3 T
CY
, before the
first SCK edge or loading SSPBUF, the peripheral
will function correctly. Also, if SSPBUF is written
prior to the SS pin going low, the peripheral will
function correctly.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
The following silicon errata apply only to
PIC18F2458/2553/4458/4553 devices with these
Device/Revision IDs:
Part Number
PIC18F2458
PIC18F2553
PIC18F4458
PIC18F4553
Device ID
0010 1010 011
0010 1010 010
0010 1010 001
0010 1010 000
Revision ID
0 0111
0 0111
0 0111
0 0111
The Device IDs (DEVID1 and DEVID2) are located at
addresses 3FFFFEh:3FFFFFh in the device’s
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.
All of the issues listed here will be addressed in future
revisions of the PIC18F2458/2553/4458/4553 silicon.
TABLE 1:
Param
No.
70
EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING)
Characteristic
Min
3 T
CY
Max Units Conditions
—
ns
Symbol
T
SS
L2
SC
H, SS
↓
to SCK
↓
or SCK
↑
Input
T
SS
L2
SC
L
©
2008 Microchip Technology Inc.
DS80387A-page 1
PIC18F2458/2553/4458/4553
2. Module: MSSP
With MSSP in SPI Master mode, F
OSC
/64 or
Timer2/2 clock rate and CKE =
0,
a write collision
may occur if SSPBUF is loaded immediately after
the transfer is complete. A delay may be required
after the MSSP Interrupt Flag bit, SSPIF, is set or
the Buffer Full bit, BF, is set and before writing
SSPBUF. If the delay is insufficiently short, a write
collision may occur as indicated by the WCOL bit
being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents. Verify the WCOL
bit is clear after writing SSPBUF. If the WCOL is
set, clear the bit in software and rewrite the
SSPBUF register.
Date Codes that pertain to this issue:
All engineering and production devices.
4. Module: Electrical Characteristics (BOR)
Certain operating conditions can move the effec-
tive Brown-out Reset (BOR) threshold outside of
the range specified in the electrical characteristics
of the device data sheet (parameter D005).
The BOR threshold has been observed to increase
with some table read operations. BOR has been
observed with 7 percent higher V
DD
than the V
BOR
value specified for a given BORV<1:0> setting.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
3. Module: ECCP (PWM Mode)
When configured for half-bridge operation with
dead band (CCPxCON<7:6> =
10),
the PWM
output may be corrupted for certain values of the
PWM duty cycle. This can occur when these
additional criteria are also met:
• A non-zero dead-band delay is specified
(PDC6:PDC0 > 0)
• The duty cycle has a value of 0 through 3, or
4n + 3 (n
≥
1)
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
DS80387A-page 2
©
2008 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
5. Module: MSSP
If the application firmware is expecting to receive
valid data – in either SPI Slave or Master mode –
the firmware must read from the SSPBUF register
before writing the next byte to transmit to SSPBUF.
If the firmware does not read from SSPBUF, the
BF bit (SSPSTAT<0>) can still be set from the pre-
vious transaction. If the BF bit is set, the incoming
data byte is blocked from transferring from the
SSPSR Shift register to the SSPBUF register. If
the firmware then reads from SSPBUF, the data
read will not match the data most recently received
on the SDI pin.
In the earlier silicon revision (B5), incoming data
bytes received on the SDI pin are always trans-
ferred from SSPSR to SSPBUF, regardless of the
state of the BF bit.
Work around
If the firmware expects to receive valid data,
always clear the BF bit by reading from SSPBUF
prior to writing to SSPBUF, even when the current
data in SSPBUF is not important. Sample work
around code, suitable for all silicon revisions, is
given in Example 1 (Assembly language) and
Example 2 (C language).
Date Codes that pertain to this issue:
All engineering and production devices.
EXAMPLE 1:
SAMPLE ASSEMBLY CODE FOR TRANSFERRING SPI DATA
WriteSPI:
BCF
PIR1, SSPIF
MOVF
SSPBUF, w
MOVLW 0xA5
MOVWF SSPBUF
;Perform read, even if the data in SSPBUF is not important
;In this example, let’s send “0xA5” to the other SPI device.
WaitXmitComplete:
BTFSS PIR1, SSPIF
BRA
WaitXmitComplete
MOVF
SSPBUF, w
;The data received should be valid.
EXAMPLE 2:
SAMPLE C CODE FOR TRANSFERRING SPI DATA
unsigned char WriteSPI(unsigned char ByteToSend)
{
unsigned char TempVariable;
PIR1bits.SSPIF = 0;
TempVariable = SSPBUF;
SSPBUF = ByteToSend;
while(!PIR1bits.SSPIF);
return SSPBUF;
}
// Reads from SSPBUF, ensures BF bit is clear before
// sending the next byte.
// Wait until the transmission is complete.
// The data received should be valid.
©
2008 Microchip Technology Inc.
DS80387A-page 3
PIC18F2458/2553/4458/4553
REVISION HISTORY
Rev A Document (8/2008)
Initial release of this document. Includes silicon issues
1-2 (MSSP), 3 (ECCP – PWM Mode), 4 (Electrical
Characteristics – BOR) and 5 (MSSP).
DS80387A-page 4
©
2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
•
•
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EE
L
OQ
, K
EE
L
OQ
logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC and SmartShunt are registered trademarks
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SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
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32
logo, PowerCal, PowerInfo,
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All other trademarks mentioned herein are property of their
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© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, K
EE
L
OQ
®
code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
©
2008 Microchip Technology Inc.
DS80387A-page 5
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