530VC90M0000DGR datasheet, PDF

Datasheet> All Categories > oscillator> 530VC90M0000DGR

530VC90M0000DGR: DescriptionCMOS Output Clock Oscillator, 90MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530VC90M0000DGR Overview

CMOS Output Clock Oscillator, 90MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530VC90M0000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	90 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS
physical size	7.0mm x 5.0mm x 1.85mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

STK4046, 4048 typical application circuit

Simple and practical uninterruptible power supply circuit

Transistor multiple "1" detection circuit

Fluorescent lamps are started by connecting diodes under low temperature conditions

Lithium-ion battery charger circuit 3

Pillow school circuit-3

How about setting up an offline laboratory?: [size=4][color=#0000ff]It's just a sudden thought. I hope the forum friends will give me some encouragement or some cold water:pleased:[/color][/size][size=4][color=#0000ff] [/color][/size] [size=4][c...; soso Talking

Ask a question about the counter program: This is the code I debugged: org 0000h ljmp star org 0003h reti org 000bh reti org 0013h reti org 001bh reti org 0023h reti a_bit equ 20h ;The ones digit is stored in b_bit equ 21h ;The tens digit is ...; chich MCU

Graduate students are confused about self-studying FPGA. Are you guys suffering from the same troubles as me?: I am a first-year graduate student. I don't like what the project team does. I like hardware, such as circuit boards, microcontrollers, and FPGAs. However, they are working on fiber optic sensors and ...; cuianbin FPGA/CPLD

[Low power consumption] Xilinx 28nm helps lower power consumption and support more applications: ...; ddllxxrr FPGA/CPLD

Open1081 usage notes--How to start STM32F205R: [align=left][color=#000000]I have always wanted to transplant the bootloader from the official original version to Open1081, so I sorted out the startup method before. [/color][/align][align=left][col...; wuyanyanke RF/Wirelessly

【Project Outsourcing】USB to multi-channel serial port data acquisition card: [Project Outsourcing] USB to multi-channel serial port data acquisition card requires the friend who takes over to be familiar with FPGA program writing and product driver writing under Windows, IC wi...; 王子花 Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components