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P3C1041-10JC

Description
HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM
Categorystorage    storage   
File Size291KB,10 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P3C1041-10JC Overview

HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM

P3C1041-10JC Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeSOJ
package instructionSOJ,
Contacts44
Reach Compliance Codecompli
ECCN code3A991.B.2.A
Maximum access time10 ns
JESD-30 codeR-PDSO-J44
JESD-609 codee0
length28.575 mm
memory density4194304 bi
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals44
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX16
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height3.7592 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
Base Number Matches1
P3C1041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 10/12/15/20 ns (Commercial)
— 12/15/20 ns (Industrial)
Low Power
— 325 mW (max.)
Single 3.3V ± 0.3V Power Supply
2.0V Data Retention
Easy Memory Expansion Using
CE
and
OE
Inputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down when deselected
Packages
—44-Pin SOJ, TSOP II
DESCRIPTION
The P3C1041 is a 262,144 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM oper-
ates from a single 3.3V ± 0.3V tolerance power
supply.
Access times as fast as 10 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P3C1041
is a member of a family of PACE RAM™ products offer-
ing fast access times.
The P3C1041 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A
0
to A
17
. Reading is
accomplished by device selection (CE and output en-
abling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either
CE
or
OE
is HIGH or
WE
is
LOW.
Package options for the P3C1041 include 44-pin SOJ
and TSOP packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1519B
SOJ
TSOP II
Document #
SRAM130
REV OR
1
Revised October 2005
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