74LVC544DB datasheet, PDF - EEWORLD Datasheet

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74LVC544DB: DescriptionIC LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, Bus Driver/Transceiver; Categorylogic; File Size157KB，5 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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74LVC544DB Overview

IC LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, Bus Driver/Transceiver

74LVC544DB Parametric

Parameter Name	Attribute value
Maker	NXP
package instruction	SSOP,
Reach Compliance Code	unknown
Other features	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G24
length	8.2 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	INVERTED
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
propagation delay (tpd)	10 ns
Certification status	Not Qualified
Maximum seat height	2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	5.3 mm
Base Number Matches	1

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74LVC544DB Related Products

	74LVC544DB	74LVC544D	74LVC544PW
Description	IC LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, Bus Driver/Transceiver	IC LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, Bus Driver/Transceiver	IC LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, Bus Driver/Transceiver
Maker	NXP	NXP	NXP
package instruction	SSOP,	SOP,	TSSOP,
Reach Compliance Code	unknown	unknown	unknown
Other features	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH
series	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24
length	8.2 mm	15.4 mm	7.8 mm
Load capacitance (CL)	50 pF	50 pF	50 pF
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
Number of digits	8	8	8
Number of functions	1	1	1
Number of ports	2	2	2
Number of terminals	24	24	24
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE
Output polarity	INVERTED	INVERTED	INVERTED
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	10 ns	10 ns	10 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2 mm	2.65 mm	1.1 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.2 V	1.2 V	1.2 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	1.27 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL
width	5.3 mm	7.5 mm	4.4 mm
Base Number Matches	1	1	1

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