DATASHEET
SYSTEM PERIPHERAL CLOCK SOURCE
Description
The ICS650-01 is a low-cost, low-jitter, high-performance
clock synthesizer for system peripheral applications. Using
analog/digital Phase-Locked Loop (PLL) techniques, the
device accepts a parallel resonant 14.31818 MHz crystal
input to produce up to eight output clocks. The device
provides clocks for PCI, SCSI, Fast Ethernet, Ethernet,
USB, and AC97. The user can select one of three USB
frequencies and also one of two AC97 audio frequencies.
The OE pin puts all outputs into a high impedance state for
board level testing. All frequencies are generated with less
than one ppm error, meeting the demands of SCSI and
Ethernet clocking.
ICS650-01
Features
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Packaged in 20-pin SSOP (QSOP)
Available in Pb (lead) free package
Operating voltage of 3.3 V or 5 V
Less than one ppm synthesis error in all clocks
Inexpensive 14.31818 MHz crystal or clock input
Provides Ethernet and Fast Ethernet clocks
Provides SCSI clocks
Provides PCI clocks
Selectable AC97 audio clock
Selectable USB clock
OE pin tri-states the outputs for testing
Selectable frequencies on three clocks
Duty cycle of 40/60
Advanced, low-power CMOS process
Industrial temperature range available
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
VDD
3
PSEL1:0
ASEL
USEL
14.31818 MHz
Crystal or Clock
X1/ICLK
2
4
Processor
Clocks
Audio Clock
USB Clock
20 MHz
Clock
Synthesis
Circuitry
Crystal
Oscillator
X2
2
GND
OE (all outputs)
14.31818 MHz
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE
1
ICS650-01
REV G 102709
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
Pin Assignment
USEL
X2
X1/ICLK
VDD
VDD
GND
UCLK
20M
ACLK
PCLK4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PSEL1
PSEL0
PCLK2
PCLK3
VDD
ASEL
GND
14.318M
PCLK1
OE
Processor Clock (MHz)
PSEL1
0
0
0
M
M
M
1
1
1
PSEL0
0
M
1
0
M
1
0
M
1
PCLK1
25
TEST
TEST
40
33.3334
20
20
20
PCLK2, 3
50
TEST
TEST
80
66.6667
40
33.3334
66.6667
PCLK4
18.75
TEST
TEST
20
25
25
25
25
Stops low all clocks except 20M
20 pin (150 mil) SSOP
Audio Clock (MHz)
USB Clock (MHz)
ASEL
USEL
0
M
1
UCLK
12
24
48
0
M
1
ACLK
49.152
24.576
12.288
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
Pin
Name
USEL
X2
X1/ICLK
VDD
VDD
GND
UCLK
20M
ACLK
PCLK4
Pin
Type
Input
XO
XI
Power
Power
Power
Output
Output
Output
Output
Pin Description
UCLK select pin. Determines frequency of USB clock per table above.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal.
Leave open for clock.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal or
clock.
Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
Connect to VDD. Must be same value as other VDD.
Connect to ground.
USB clock output per table above.
Fixed 20 MHz output for Ethernet. Only clock that runs when
PSEL1=PSEL0=1.
AC97 audio clock output per table above.
PCLK output number 4 per table above.
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE
2
ICS650-01
REV G 102709
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
Pin
Number
11
12
13
14
15
16
17
18
19
20
Pin
Name
OE
PCLK1
14.318M
GND
ASEL
VDD
PCLK3
PCLK2
PSEL0
PSEL1
Pin
Type
Input
Output
Output
Power
Input
Power
Output
Output
Input
Input
Pin Description
Output enable. Tri-states all outputs when low.
PCLK output number 1 per table above.
14.31818 MHz Buffered reference clock output.
Connect to ground.
ACLK select pin. Determines frequency of Audio clock per table above.
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
PCLK output number 3 per table above.
PCLK output number 2 per table above.
Processor select pin #0. Determines frequencies on PCLKs 1-4 per table
above.
Processor select pin #1. Determines frequencies on PCLKs 1-4 per table
above.
External Components
The ICS650-01 requires a minimum number of external
components for proper operation.
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω
.
Decoupling Capacitor
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant, 300 ppm or better (to
meet Ethernet specs). Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Crystal caps (pF) = (C
L
- 12) x 2
In the equation, C
L
is the crystal load capacitance. So, for a
crystal with a 16 pF load capacitance, two 8 pF capacitors
should be used. If a clock input is used, drive it into X1 and
leave X2 unconnected.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock line,
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE
3
ICS650-01
REV G 102709
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
+3.3
Max.
+70
+5.5
Units
°
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5% (or 5 V unless noted),
Ambient Temperature 0 to +70° C
Parameter
Operating Voltage
Supply Current
Supply Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance
Symbol
VDD
IDD
IDD
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
Conditions
At 5 V, No load, Note 1
At 3.3 V, No load,
Note 1
Select inputs, OE
Select inputs, OE
VDD = 3.3 V,
I
OH
= -8 mA
VDD = 3.3 V or 5 V,
I
OH
= -8 mA
VDD = 3.3 V,
I
OL
= 8mA
VDD = 3.3 V,
each output
Except X1
Min.
3.0
Typ.
50
30
Max.
5.5
Units
V
mA
mA
V
2
0.8
2.4
VDD-0.4
0.4
±50
7
V
V
V
V
mA
pF
Note 1: With all clocks at highest frequencies.
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE
4
ICS650-01
REV G 102709
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5% (or 5 V unless noted),
Ambient Temperature 0 to +70° C
Parameter
Input Frequency
Output Clocks Accuracy
(synthesis error)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
One Sigma Jitter
Absolute Clock Period Jitter
Symbol
Conditions
All clocks
Min.
Typ.
14.31818
Max. Units
MHz
1
ppm
ns
ns
60
%
ps
ps
500
ps
t
OR
t
OF
0.8 to 2.0 V, Note 1
2.0 to 0.8 V, Note 1
At VDD/2
except ACLK
ACLK
PCLK, UCLK, 20M
-500
40
1.5
1.5
50
75
170
Note 1: Measured with 15 pF load
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
135
93
78
60
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE
5
ICS650-01
REV G 102709
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