531QA549M000DGR datasheet, PDF

Datasheet> All Categories > oscillator> 531QA549M000DGR

531QA549M000DGR: DescriptionCMOS/TTL Output Clock Oscillator, 549MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531QA549M000DGR Overview

CMOS/TTL Output Clock Oscillator, 549MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531QA549M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	549 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Photodiode isolation amplifier circuit diagram composed of ISO212P

Network card power supply circuit using SC1470 control chip

Small degausser circuit

KJZ6 type three-phase fully controlled bridge trigger control circuit

LT1111 working principle diagram (b)

555 high voltage mosquito killer circuit

I'm wondering if anyone has used a similar switch?: [i=s]This post was last edited by Alex1126 on 2020-3-8 11:13[/i]Now there is a demand: the equipment is powered by 9-32V DC, and the equipment is small and there is no space to install a switch. I wan...; Alex1126 Integrated technical exchanges

Currently bidding: Zhou Ligong TinyM0 September 14th 12:00-September 15th 11:59: [size=4][color=#ff0000][b]Bidding dynamics: Starting price 1000 core coins[/b][/color][/size] [hr][size=4] This event is supported by [url=https://bbs.eeworld.com.cn/thread-511067-1-1.html]EEWORLD Dev...; okhxyyo Talking

【Signal Processing】Implementation and application of a radar general signal processing system: Abstract: In view of the respective advantages of FPGA and DSP, FPGA+DSP signal processing architecture has become a common structure of signal processing systems. However, the current processing plat...; cillyfly FPGA/CPLD

Some issues of microblaze: Is there any tutorial for building a project? I built it according to the tutorial on the official website (I used ise13.1), but I was frustrated. The following problems I encountered: 1. Header file ...; 乱起东城 FPGA/CPLD

Analog multiplier (checked): [i=s] This post was last edited by Xin Xin on 2018-4-8 22:59 [/i] [b][color=#008000]I actually never picked up this thing later. [/color][/b] [color=#008000][b]But, there is no need to think about it....; 辛昕 Analog electronics

Creating Windows CE Operating System (Part 2): Previously, we introduced how to create a basic Windows CE platform. Now let's customize the parts that were not mentioned last time and build the OS. First, in View -> Other Windows -> Catalog Items ...; 星空世界 Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components