IDT71V3577YS80PFGI8 datasheet, PDF

Datasheet> All Categories > storage> storage> IDT71V3577YS80PFGI8

IDT71V3577YS80PFGI8: DescriptionStandard SRAM, 128KX36, 8ns, CMOS, PQFP100; Categorystorage storage; File Size233KB，22 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

Download Datasheet Parametric View All

IDT71V3577YS80PFGI8 Overview

Standard SRAM, 128KX36, 8ns, CMOS, PQFP100

IDT71V3577YS80PFGI8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Reach Compliance Code	unknown
Maximum access time	8 ns
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e3
memory density	4718592 bit
Memory IC Type	STANDARD SRAM
memory width	36
Humidity sensitivity level	3
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum standby current	0.035 A
Minimum standby current	3.14 V
Maximum slew rate	0.21 mA
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
Base Number Matches	1

Preview

Download Datasheet

View All

128K X 36, 256K X 18

3.3V Synchronous SRAMs

3.3V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

Features

◆

IDT71V3577YS

IDT71V3579YS

IDT71V3577YSA

IDT71V3579YSA

Description

The IDT71V3577/79 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,

address and control registers. There are no registers in the data output

path (flow-through architecture). Internal logic allows the SRAM to gen-

erate a self-timed write based upon a decision which can be left until the

end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V3577/79 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will flow-through from the

array after a clock-to-data access time delay from the rising clock edge of

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequent three cycles of output data will be available to the user on the

next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the

LBO

input pin.

The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

◆

128K x 36, 256K x 18 memory configurations

Supports fast access times:

Commercial:

– 6.5ns up to 133MHz clock frequency

– 7.5ns up to 117MHz clock frequency

Commercial and Industrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

NOTE:

and

are not applicable for the IDT71V3579.

APRIL 2006

DSC-6450/0A

6450tbl 01

Recommended Resources

Capacitance measuring instrument circuit

AC input automatic switching and rectification circuit diagram

Linear variable differential transformer drive demodulator circuit diagram

AC trigger delay control circuit

555 two-stage sequential timer circuit

Computer motherboard circuit diagram 810 2_01

Five design issues for telemedicine patient monitoring systems: [i=s]This post was last edited by qwqwqw2088 on 2021-4-15 09:10[/i]The wearable patient monitor market is growing rapidly. Remote patient monitors help doctors monitor patients in real time, which for...; qwqwqw2088 Analogue and Mixed Signal

Raspberry 3 Unboxing: The latest Raspberry Pi 3 just received, unboxing and display...; qwerghf Linux and Android

What is the format and value of the car door switch signal transmitted on the CAN bus?: What is the format and value of the car door switch signal transmitted on the CAN bus?...; fy6033093 Automotive Electronics

【New Year, New Plan】 Work hard to recharge and change your life.: When I just graduated from college, my lazy attitude made me waste a lot of time. Now I am back to the research and development work I like. I hope I can recharge myself and change my life in the new ...; Milo.Bai Talking

Analog Switches in Audio Applications (TI): Analog Switches in Audio Applications, presented by Product Engineer Guoda Lian. For more analog products and related information, please visit: www.ti.com/analognewsletter[flash]http://player.youku.c...; 德州仪器_视频 Analog electronics

Ask about digital IC verification: Hello everyone, I recently applied for a digital IC verification internship position. I have always been interested in digital IC design and want to work in this field in the future. I would like to a...; wangxichao FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components