ASM4SSTVF16859-56QR datasheet, PDF

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ASM4SSTVF16859-56QR: DescriptionD Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PQCC56, MLF2-56; Categorylogic; File Size163KB，16 Pages; ManufacturerPulseCore Semiconductor Corporation

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ASM4SSTVF16859-56QR Overview

D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PQCC56, MLF2-56

ASM4SSTVF16859-56QR Parametric

Parameter Name	Attribute value
Maker	PulseCore Semiconductor Corporation
package instruction	HVQCCN,
Reach Compliance Code	unknown
series	SSTV
JESD-30 code	S-PQCC-N56
JESD-609 code	e0
length	8 mm
Logic integrated circuit type	D FLIP-FLOP
Number of digits	13
Number of functions	1
Number of terminals	56
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	2.8 ns
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	8 mm
minfmax	210 MHz
Base Number Matches	1

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August 2004

rev 2.0

DDR 13-Bit to 26-Bit Registered Buffer

ASM4SSTVF16859

off. Note that RESETB should be supported with a

Features



Differential clock signals.

Meets SSTL_2 class II specifications on

outputs.



Low voltage operation: V

= 2.3V to 2.7V.

Available in 64-pin TSSOP, 64-pin TVSOP,

and 56-pin VFQFN packages.

LVCMOS level at a valid state since VREF may not be

stable during power-up.

To ensure that outputs are at a defined logic state before a

stable clock has been supplied, RESETB must be held at a

logic low level during power-up.

Product Description

The ASM4SSTVF16859 is a universal 13/26 bit

(D F/F based), designed for 2.3V to 2.7V

In the JEDEC defined Registered DDR DIMM application,

RESETB is specified to be asynchronous with respect to

CLK/CLKB; therefore, no timing relationship can be

guaranteed between the two signals. When entering a

low-power standby state, the register will be cleared and

the outputs will be driven to a logic low level quickly

relative to the time to disable the differential input

receivers. This ensures there are no “glitches” on any

output. However, when coming out of low power standby

mode, the register will become active quickly relative to the

time taken to enable the differential input receivers. When

the data inputs are at a logic level low and the clock is

stable during the low-to-high transition of RESETB until the

operation. The device supports SSTL_2 I/O

levels, and is fully compliant with the JEDEC JC40,

JC42.5 DDR I specifications covering PC1600, PC

2100, PC2700, and PC3200 operational ranges ( DDR

400

– 200 MHz ). 13/26 bits refers to 2Q outputs for

each D input - designed for use in Stacked Registered

(stacked

Memory

Devices),

Buffered

DIMM

applications.

Data flow from D to Q is controlled by the differential

clock (CLK/CLKB) and a control signal (RESETB).

The positive edge of CLK is used to trigger the data

transfer, and CLKB is used to maintain sufficient noise

margins, whereas RESETB input is designed and

intended for use at power-up.

input receivers are fully enabled, the design ensures that

the outputs will remain at a logic low level.

Applications

•

JEDEC and Non-JEDEC DDR Memory Modules

•

Stacked or Planar configurations.

Supports PC1600 - PC2100 - PC2700 - PC3200

•

DDR 400 compliant (200MHz+).

The ASM4SSTVF16859 supports a low power standby

mode of operation. A logic level low at RESETB,

assures that all internal registers and outputs (Q) are

reset to a logic low state, and that all input receivers,

data (D) buffers, and clock (CLK/CLKB) are switched

SSTL_2 I/O.

Provides a complete support solution for JEDEC

JC42.5 DIMMs’ when used with the ASM5CVF857

Zero Delay Buffer.

Alliance Semiconductor

2575, Augustine Drive



Santa Clara, CA



Tel: 408.855.4900



Fax: 408.855.4999



www.alsc.com

Notice: The information in this document is subject to change without notice.

ASM4SSTVF16859-56QR Related Products

	ASM4SSTVF16859-56QR	ASM4SSTVF16859-64TR	ASM4SSTVF16859-56QT	ASM4SSTVF16859-64TT
Description	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PQCC56, MLF2-56	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PDSO64, 0.240 INCH, 0.50 MM PITCH, TSSOP-64	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PQCC56, MLF2-56	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PDSO64, 0.240 INCH, 0.50 MM PITCH, TSSOP-64
Maker	PulseCore Semiconductor Corporation	PulseCore Semiconductor Corporation	PulseCore Semiconductor Corporation	PulseCore Semiconductor Corporation
package instruction	HVQCCN,	TSSOP,	MLF2-56	TSSOP,
Reach Compliance Code	unknown	unknown	unknown	unknown
series	SSTV	SSTV	SSTV	SSTV
JESD-30 code	S-PQCC-N56	R-PDSO-G64	S-PQCC-N56	R-PDSO-G64
JESD-609 code	e0	e0	e0	e0
length	8 mm	17 mm	8 mm	17 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Number of digits	13	13	13	13
Number of functions	1	1	1	1
Number of terminals	56	64	56	64
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
Output polarity	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVQCCN	TSSOP	HVQCCN	TSSOP
Package shape	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
propagation delay (tpd)	2.8 ns	2.8 ns	2.8 ns	2.8 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1 mm	1.2 mm	1 mm	1.2 mm
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	NO LEAD	GULL WING	NO LEAD	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	DUAL	QUAD	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	8 mm	6.1 mm	8 mm	6.1 mm
minfmax	210 MHz	210 MHz	210 MHz	210 MHz
Base Number Matches	1	1	1	-

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