74F533 Octal Transparent Latch with 3-STATE Outputs
April 1988
Revised October 2000
74F533
Octal Transparent Latch with 3-STATE Outputs
General Description
The 74F533 consists of eight latches with 3-STATE outputs
for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state. The 74F533 is the same as the
74F373, except that the outputs are inverted.
Features
s
Eight latches in a single package
s
3-STATE outputs for bus interfacing
s
Inverted version of the 74F373
Ordering Code:
Order Number
74F533SC
74F533SJ
74F533PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS009548
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74F533
Unit Loading/Fan Out
U.L.
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary 3-STATE Outputs
Description
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
−
3 mA/24 mA (20 mA)
Function Table
Inputs
LE
H
H
L
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Functional Description
Output
D
H
L
X
X
O
L
H
O
0
Z
The 74F533 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
OE
L
L
L
H
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F533
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
BVIT
I
CEX
V
ID
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCZ
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I/O)
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
41
−60
4.75
3.75
−0.6
50
−50
−150
500
61
10% V
CC
2.5
2.4
2.7
2.7
0.5
5.0
7.0
0.5
50
V
µA
µA
mA
µA
V
µA
mA
µA
µA
mA
µA
mA
Min
Max
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0V
Max
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OL
=
24 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
IN
=
5.5V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
OUT
=
2.7V
V
OUT
=
0.5V
V
OUT
=
0V
V
OUT
=
5.25V
V
O
=
HIGH Z
3
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74F533
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
4.0
2.5
5.0
3.0
2.0
2.0
1.5
1.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
6.7
4.4
7.1
4.7
5.9
5.6
3.4
2.7
Max
9.0
7.0
11.0
7.0
10.0
7.5
6.5
5.5
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
4.0
2.5
5.0
3.0
2.0
2.0
1.5
1.5
Max
12.0
9.0
14.0
9.0
12.5
10.5
8.5
7.5
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
4.0
2.5
5.0
3.0
2.0
2.0
1.5
1.5
Max
10.0
8.0
13.0
8.0
11.0
8.5
7.0
6.5
ns
ns
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width, HIGH
2.0
2.0
3.0
3.0
6.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
Min
2.0
2.0
3.0
3.0
6.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
2.0
2.0
3.0
3.0
6.0
Max
ns
ns
ns
Units
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74F533
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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