FemtoClock
®
Crystal-to-0.7V Differential
HCSL Clock Generator
ICS841402I
DATA SHEET
General Description
The ICS841402I is an optimized PCIe and sRIO clock generator.
The device uses a 25MHz parallel resonant crystal to generate
100MHz, 125MHz, 200MHz and 400MHz clock signals, replacing
solutions requiring multiple oscillator and fanout buffer solutions. The
device has excellent phase jitter suitable to clock components
requiring precise and low jitter PCIe, sRIO or both clock signals. The
device also supports a configurable spread-spectrum generation for
PCIe applications. Designed for telecom, networking and industrial
applications, the ICS841402I can also drive the high-speed sRIO
and PCIe SerDes clock inputs of communications processors,
DSPs, switches and bridges.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Two 0.7V differential HCSL outputs: configurable for PCIe
(100MHz or 200MHz) and sRIO (125MHz) clock signals
One LVCMOS/LVTTL reference clock output
Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference clock
input
Supports the following output frequencies: 100MHz, 125MHz,
200MHz or 400MHz
VCO frequency range: 950MHz - 1.25GHz
Configurable spread-spectrum generation for PCIe
PLL bypass and output enable
RMS phase jitter @ 200MHz, using a 25MHz crystal
(12kHz – 20MHz): 1.21ps (typical)
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant (REF_OUT disabled)
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Block Diagram
OE_REFOUT
Pulldown
25MHz
REF_OUT
25MHz
XTAL_IN
OSC
XTAL_OUT
REF_IN
Pulldown
0
1
FemtoClock
PLL
1
Spread-Spectrum
0
N
=
÷
÷
÷
÷
Q0
nQ0
Q1
nQ1
REF_SEL
Pulldown
Pin Assignment
REF_SEL
BYPASS
REF_IN
GND
IREF
SSM
V
DDA
V
DD
M=
÷40,
÷
48
IREF
SSM
BYPASS
FSEL[1:0]
MR/nOE
Pulldown
Pulldown
Pullup:Pulldown
Pulldown
32 31 30 29 28 27 26 25
2
XTAL_IN
XTAL_OUT
MR/nOE
V
DD
Q0
nQ0
Q1
nQ1
1
2
3
4
5
6
7
8
24
V
DD
FSEL1
FSEL0
REF_OUT
OE_REFOUT
GND
nc
nc
ICS841402I
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
9 10 11 12 13 14 15 16
V
DD
nc
GND
nc
nc
nc
nc
nc
23
22
21
20
19
18
17
ICS841402DKI REVISION A NOVEMBER 7, 2012
1
©2012 Integrated Device Technology, Inc.
ICS841402I Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1,
2
3
4, 14, 24, 29
5, 6
7, 8
9, 19, 32
10, 11, 12,
13, 15, 16,
17, 18
20
21
22
23
25
Name
XTAL_IN,
XTAL_OUT
MR/nOE
V
DD
Q0, nQ0
Q1, nQ1
GND
nc
OE_REFOUT
REF_OUT
F_SEL0
F_SEL1
SSM
Input
Input
Power
Output
Output
Power
Unused
Input
Output
Input
Input
Input
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Type
Description
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input. (PLL reference.)
Master reset. LVCMOS/LVTTL interface levels. See Table 3D.
Core supply pins.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Power supply ground.
No connect.
Output enable pin. LVCMOS/LVTTL interface levels. See Table 3F.
Reference clock output. LVCMOS/LVTTL interface levels. In PCIe Gen 2
and Gen 3 applications, the REF_OUT output should be disabled.
Output frequency select pin. LVCMOS/LVTTL interface levels.
See Table 3B.
Output frequency select pin. LVCMOS/LVTTL interface levels.
See Table 3B.
Spread-spectrum selection. LVCMOS/LVTTL interface levels.
See Table 3A.
0.7V current reference resistor output. A fixed precision resistor (475
)
from this pin to ground provides a reference current used for differential
current-mode Qx, nQx clock outputs.
Pulldown
Selects PLL operation/PLL bypass operation. See Table 3C.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown
Pulldown
Reference select. Selects the input reference source.
LVCMOS/LVTTL interface levels. See Table 3E.
LVCMOS/LVTTL PLL reference clock input.
26
IREF
Output
27
28
30
31
BYPASS
V
DDA
REF_SEL
REF_IN
Input
Power
Input
Input
NOTE:
Pulldown
and
Pullup
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
R
OUT
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Output
Impedance
REF_OUT
Test Conditions
Minimum
Typical
4
51
51
27
Maximum
Units
pF
k
k
ICS841402DKI REVISION A NOVEMBER 7, 2012
2
©2012 Integrated Device Technology, Inc.
ICS841402I Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR
Function Tables
Table 3A. Spread-Spectrum Modulation (SSM) Function Table (f
REF
= 25MHz)
Input
SSM
0
1
Outputs
Q[0:1], nQ[0:1]
SSM off (default)
SSM on (at 32kHz, -0.5%)
Table 3B. FSEL Function Table (f
REF
= 25MHz)
Inputs
FSEL1
0
0
1
1
FSEL0
0
1
0
1
M Divider
48
40
48
48
N Divider
12
8
6
3
Outputs
Q[0:1], nQ[0:1]
VCO/12 (100MHz) PCIe
VCO/8 (125MHz) sRIO
VCO/6 (200MHz) PCIe (default)
VCO/3 (400MHz)
Table 3C. BYPASS Function Table
Input
BYPASS
0
1
PLL Configuration
PLL on (default)
PLL bypassed (Q[0:1], nQ[0:1] = f
REF
/N)
Table 3E. REF_SEL Function Table
Input
REF_SEL
0
1
Input Reference
XTAL (default)
REF_IN
Table 3D. MR/nOE Function Table
Input
MR/nOE
0
1
Function
NOTE1
Outputs enabled (default)
Device reset, outputs disabled (High Impedance)
Table 3F. OE_REFOUT Function Table
Input
OE_REFOUT Function
0
1
REF_OUT disabled (High Impedance) (default)
REF_OUT enabled
NOTE 1: Asynchronous function.
ICS841402DKI REVISION A NOVEMBER 7, 2012
3
©2012 Integrated Device Technology, Inc.
ICS841402I Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
37.0C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Power Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Outputs unterminated
Outputs unterminated
Test Conditions
Minimum
3.135
V
DD
– 0.16
Typical
3.3
3.3
Maximum
3.465
V
DD
156
16
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
REF_IN, REF_SEL,
BYPASS, SSM,
F_SEL0, MR/nOE,
OE_REFOUT
F_SEL1
REF_IN, REF_SEL,
BYPASS, SSM,
F_SEL0, MR/nOE,
OE_REFOUT
F_SEL1
V
OH
V
OL
Output High
Voltage
Output Low
Voltage
REF_OUT
REF_OUT
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.5
Units
V
V
I
IH
Input High
Current
V
DD
= V
IN
= 3.465V
150
µA
V
DD
= V
IN
= 3.465V
5
µA
I
IL
Input Low
Current
V
DD
= 3.465V, V
IN
= 0V
-5
µA
V
DD
= 3.465V, V
IN
= 0V
I
OH
= -12mA
I
OL
= 12mA
-150
2.6
0.5
µA
V
V
ICS841402DKI REVISION A NOVEMBER 7, 2012
4
©2012 Integrated Device Technology, Inc.
ICS841402I Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
pF
AC Electrical Characteristics
Table 6A. PCI Express Jitter Specifications,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
t
j
(PCIe Gen 1)
t
REFCLK_HF_RMS
(PCIe Gen 2)
t
REFCLK_LF_RMS
(PCIe Gen 2)
t
REFCLK_LF_RMS
(PCIe Gen 3)
Parameter
Phase Jitter
Peak to Peak
Note 1, 4
Phase Jitter
RMS;
NOTE 2, 4
Phase Jitter
RMS;
NOTE 2, 4
Phase Jitter
RMS;
NOTE 3, 4
Test Conditions
ƒ = 100MHz, 25MHz crystal input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ = 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ = 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
ƒ = 100MHz, 25MHz crystal input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum
Typical
14.2
Maximum
30.6
PCIe Industry
Specification
86
Units
ps
0.77
1.4
3.1
ps
0.17
0.45
3.0
ps
0.16
0.35
0.8
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the
PCI Express Application Note section
in the datasheet.
NOTE: PCIe jitter parameters were obtained with Spread Spectum Modulation disabled.
NOTE: PCIe Gen 2 and Gen 3 jitter parameters were obtained with REF_OUT disabled.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10
6
clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
REFCLK_HF_RMS
(High Band) and 3.0ps RMS for t
REFCLK_LF_RMS
(Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the
PCI Express
Base Specification Revision 0.7, October 2009
and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
ICS841402DKI REVISION A NOVEMBER 7, 2012
5
©2012 Integrated Device Technology, Inc.
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