TECHNICAL DATA
KK74ACT273
Octal D Flip-Flop with
Common Clock and Reset
High-Speed Silicon-Gate CMOS
The KK74ACT273 is identical in pinout to the LS/ALS273,
HC/HCT273. The KK74ACT273 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of eight D flip-flops with common Clock and
Reset inputs. Each flip-flop is loaded with a low-to-high transition of the
Clock input. Reset is asynchronous and active low.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0
µA;
0.1
µA
@ 25°C
•
Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74ACT273N Plastic
KK74ACT273DW SOIC
T
A
= -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Reset
L
PIN 20=V
CC
PIN 10 = GND
H
H
H
H
X = don’t care
L
Clock
X
D
X
H
L
X
X
Output
Q
L
H
L
no change
no change
1
KK74ACT273
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±20
±50
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
J
T
A
I
OH
I
OL
t
r
, t
f
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Junction Temperature (PDIP)
Operating Temperature, All Package Types
Output Current - High
Output Current - Low
Input Rise and Fall Time
*
(except Schmitt Inputs)
V
CC
=4.5 V
V
CC
=5.5 V
Min
4.5
0
-40
Max
5.5
V
CC
140
+85
-24
24
Unit
V
V
°C
°C
mA
mA
ns/V
0
0
10
8.0
V
IN
from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
KK74ACT273
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-
Level Output Voltage
Test Conditions
V
OUT
=0.1 V or V
CC
-0.1 V
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
-50
µA
V
IN
=V
IH
or V
IL
I
OH
=-24 mA
I
OH
=-24 mA
V
OL
Maximum Low-
Level Output Voltage
I
OUT
≤
50
µA
*
*
Guaranteed Limits
25
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
-40°C to
85°C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
1.5
75
-75
8.0
80
µA
mA
mA
mA
µA
V
Unit
V
V
V
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
5.5
5.5
5.5
5.5
V
IN
=V
IH
or V
IL
I
OL
=24 mA
I
OL
=24 mA
V
IN
=V
CC
or GND
V
IN
=V
CC
- 2.1 V
V
OLD
=1.65 V Max
V
OHD
=3.85 V Min
V
IN
=V
CC
or GND
I
IN
∆I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Additional Max
I
CC
/Input
+Minimum Dynamic
Output Current
+Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
(per Package)
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
3
KK74ACT273
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Symbol
f
max
t
PHL
t
PLH
t
PHL
C
IN
Parameter
Maximum Clock Frequency (Figure 1)
Propagation Delay, Clock to Q (Figure 1)
Propagation Delay, Clock to Q (Figure 1)
Propagation Delay, Reset to Q (Figure 2)
Maximum Input Capacitance
25
°C
Min
125
3.0
3.0
3.0
4.5
10.0
11.0
11.0
Max
-40°C to 85°C
Min
125
2.5
2.5
2.5
4.5
11.0
12.0
11.5
Max
MHz
ns
ns
ns
pF
Unit
Typical @25°C,V
CC
=5.0 V
C
PD
Power Dissipation Capacitance
50
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF, Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Symbol
t
su
t
h
t
w
t
w
t
rec
Parameter
Minimum Setup Time, Data to Clock
(Figure 3)
Minimum Hold Time, Data to Clock
(Figure 3)
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width, Reset (Figure 2)
Minimum Recovery Time, Reset to Clock
(Figure 2)
25
°C
4.5
2.0
4.0
4.0
2.0
-40°C to
85°C
5.5
2.0
4.5
4.5
3.0
Unit
ns
ns
ns
ns
4
KK74ACT273
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
EXPANDED LOGIC DIAGRAM
5
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